Andrew Lines - RankMe

18 papers Journal 4Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Clock Generator with Clock Domain Crossing. ASYNC Robert Karmazin, Andrew Lines, Prasad Joshi, Benjamin Hill
2025	—	`conf`	Mount Sisyphus: Energy-Efficient Asynchronous RISC-V Microcontroller in Intel 3 Process. ASYNC Andrew Lines, Ruokun Liu
2021	—	`conf`	Asynchronous Serial Infrastructure Using FPIO. ASYNC Andrew Lines
2018	—	`conf`	A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. VLSI Circuits Suhwan Kim, Vaibhav A. Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James W. Tschanz, Vivek De
2018	—	`conf`	Loihi Asynchronous Neuromorphic Research Chip. ASYNC Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies
2018	J	`jnl`	Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham N. Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios D. Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steven McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, Hong Wang
2014	—	`conf`	A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. ASYNC Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel
2014	J	`jnl`	Performance-Driven Clustering of Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Georgios D. Dimou, Peter A. Beerel, Andrew Lines
2013	—	`conf`	NanoMesh: An Asynchronous Kilo-Core System-on-Chip. ASYNC Jonathan Tse, Andrew Lines
2011	—	`conf`	Performance-Driven Clustering of Asynchronous Circuits. PATMOS Georgios D. Dimou, Peter A. Beerel, Andrew Lines
2011	J	`jnl`	Proteus: An ASIC Flow for GHz Asynchronous Designs. IEEE Des. Test Comput. Peter A. Beerel, Georgios D. Dimou, Andrew Lines
2009	—	`conf`	GHz Asynchronous SRAM in 65nm. ASYNC Jonathan Dama, Andrew Lines
2007	—	`conf`	The Vortex: A Superscalar Asynchronous Processor. ASYNC Andrew Lines
2006	—	`conf`	Slack Matching Asynchronous Designs. ASYNC Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies
2004	J	`jnl`	Asynchronous Interconnect for Synchronous SoC Design. IEEE Micro Andrew Lines
2003	—	`conf`	Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs. Hot Interconnects Andrew Lines
1997	—	`conf`	The Design of an Asynchronous MIPS R3000 Microprocessor. ARVLSI Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings
1994	—	`conf`	An asynchronous pipelined lattice structure filter. ASYNC Uri Cummings, Andrew Lines, Alain J. Martin