Andrew E. Caldwell

20 papers A* 5A 1Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2004 J jnl
Effective iterative techniques for fingerprinting design IP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
2003 J jnl
Hierarchical whitespace allocation in top-down placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2002 J jnl
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms.
IEEE Des. Test Comput.
Andrew E. Caldwell, Igor L. Markov
2000 — conf
Admissibility Proofs for the LCS* Algorithm.
IBERAMIA-SBIA
Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng
2000 A* conf
Can recursive bisection alone produce routable placements?
DAC
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000 J jnl
Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning.
ACM J. Exp. Algorithmics
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000 A* conf
GTX: the MARCO GSRC technology extrapolation system.
DAC
Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
2000 J jnl
Hypergraph partitioning with fixed vertices [VLSI CAD].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000 — conf
Improved algorithms for hypergraph bipartitioning.
ASP-DAC
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000 J jnl
Iterative Partitioning with Varying Node Weights.
VLSI Design
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000 J jnl
Optimal partitioners and end-case placers for standard-cell layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999 J jnl
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.
VLSI Design
Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz
1999 A conf
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning.
ALENEX
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999 A* conf
Effective Iterative Techniques for Fingerprinting Design IP.
DAC
Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
1999 A* conf
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.
DAC
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
1999 A* conf
Hypergraph Partitioning with Fixed Vertices.
DAC
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999 J jnl
On wirelength estimations for row-based placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
1999 — conf
Optimal partitioners and end-case placers for standard-cell layout.
ISPD
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999 — conf
Partitioning with terminals: a "new" problem and new benchmarks.
ISPD
Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1998 — conf
On wirelength estimations for row-based placement.
ISPD
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky