Andrew C. Ling

26 papers A* 2A 6B 3C 1Journal 5Unranked 9

Year	Rank	Type	Title / Venue / Authors
2022	A*	`conf`	A software-defined tensor streaming multiprocessor for large-scale machine learning. ISCA Dennis Abts, Garrin Kimmell, Andrew C. Ling, John Kim, Matthew Boyd, Andrew Bitar, Sahil Parmar, Ibrahim Ahmed, Roberto DiCecco, David Han, John Thompson, Michael Bye, Jennifer Hwang, Jeremy Fowers, Peter Lillian, Ashwin Murthy, Elyas Mehtabuddin, Chetan Tekur, Thomas Sohmers, Kris Kang, Stephen Maresh, Jonathan Ross
2022	—	`conf`	Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors. DSN (Supplements) Dennis Abts, Ibrahim Ahmed, Andrew Bitar, Matthew Boyd, John Kim, Garrin Kimmell, Andrew C. Ling
2022	—	`conf`	The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overview. HCS Dennis Abts, John Kim, Garrin Kimmell, Matthew Boyd, Kris Kang, Sahil Parmar, Andrew C. Ling, Andrew Bitar, Ibrahim Ahmed, Jonathan Ross
2018	B	`conf`	DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. FPL Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
2018	J	`jnl`	DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. CoRR Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
2018	—	`conf`	Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah
2018	—	`conf`	Harnessing Numerical Flexibility for Deep Learning on FPGAs. HEART Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu
2018	A	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018	B	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2017	J	`jnl`	An OpenCL(TM) Deep Learning Accelerator on Arria 10. CoRR Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
2017	A	`conf`	An OpenCL™ Deep Learning Accelerator on Arria 10. FPGA Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
2017	—	`conf`	Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. IWOCL Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu
2017	—	`conf`	Customizable FPGA OpenCL matrix multiply design template for deep neural networks. FPT Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra
2017	—	`conf`	Harnessing the Power of FPGAs with the Intel FPGA SDK for OpenCL™. IWOCL Byron Sinclair, Andrew C. Ling, Genady Paikin
2013	A	`conf`	Harnessing the power of FPGAs using altera's OpenCL compiler. FPGA Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling
2011	J	`jnl`	Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu
2010	A	`conf`	Towards scalable placement for FPGAs. FPGA Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu
2009	A	`conf`	Towards automated ECOs in FPGAs. FPGA Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
2008	—	`conf`	Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2008	J	`jnl`	Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2007	—	`conf`	BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2007	J	`jnl`	FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2007	C	`conf`	Incremental placement for structured ASICs using the transportation problem. VLSI-SoC Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	A	`conf`	FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	B	`conf`	FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	A*	`conf`	FPGA technology mapping: a study of optimality. DAC Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown