Andrew B. Kahng

540 papers A* 68A 88B 3C 22Misc 9Journal 170Unranked 172

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration. CoRR Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon
2026	—	`conf`	Au-MEDAL: Adaptable Grid Router with Metal Edge Detection And Layer Integration. ASP-DAC Andrew B. Kahng, Seokhyeong Kang, Sehyeon Kim, Jakang Lee, Dooseok Yoon
2026	J	`jnl`	Automated QoR improvement in OpenROAD with coding agents. CoRR Amur Ghose, Junyeong Jang, Andrew B. Kahng, Jakang Lee
2026	—	`conf`	Invited: Agentic AI for Physical Design R&D: Status and Prospects. ISPD Amur Ghose, Andrew B. Kahng, Sayak Kundu, Bodhisatta Pramanik
2026	—	`conf`	Invited: Post-Placement Buffering and Sizing Contest. ISPD Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Yiting Liu, Davit Markarian, SeongHyeon Park, Zhiang Wang
2026	—	`conf`	Invited: The Many PD Faces of Professor Jens Lienig. ISPD Andrew B. Kahng
2026	—	`conf`	Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research. ISPD Liwen Jiang, Andrew B. Kahng, Zhiang Wang, Zhiyu Zheng
2026	J	`jnl`	Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research. CoRR Liwen Jiang, Andrew B. Kahng, Zhiang Wang, Zhiyu Zheng
2025	Misc	`conf`	A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. FCCM Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib
2025	J	`jnl`	ArtNet: Hierarchical Clustering-Based Artificial Netlist Generator for ML and DTCO Application. CoRR Andrew B. Kahng, Seokhyeong Kang, SeongHyeon Park, Dooseok Yoon
2025	J	`jnl`	ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems. CoRR Alexander Graening, Puneet Gupta, Andrew B. Kahng, Bodhisatta Pramanik, Zhiang Wang
2025	J	`jnl`	DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Zhiang Wang
2025	A	`conf`	Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem. ICCAD Vidya A. Chhabria, Amur Ghose, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Zhiang Wang, Bing-Yue Wu
2025	—	`conf`	Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research. ISPD Vidya A. Chhabria, Jiang Hu, Andrew B. Kahng, Sachin S. Sapatnekar
2025	—	`conf`	ORFS-agent: Tool-Using Agents for Chip Design Optimization. MLCAD Amur Ghose, Andrew B. Kahng, Sayak Kundu, Zhiang Wang
2025	J	`jnl`	ORFS-agent: Tool-Using Agents for Chip Design Optimization. CoRR Amur Ghose, Andrew B. Kahng, Sayak Kundu, Zhiang Wang
2025	J	`jnl`	Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators. ACM Trans. Design Autom. Electr. Syst. Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
2025	—	`conf`	Recursive Learning-Based Virtual Buffering for Analytical Global Placement. MLCAD Andrew B. Kahng, Yiting Liu, Zhiang Wang
2025	J	`jnl`	Recursive Learning-Based Virtual Buffering for Analytical Global Placement. CoRR Andrew B. Kahng, Yiting Liu, Zhiang Wang
2025	A	`conf`	SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing. ICCAD Chung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin
2025	—	`conf`	Use Cases and Deployment of ML in IC Physical Design. ASP-DAC Amur Ghose, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Bodhisatta Pramanik, Zhiang Wang, Dooseok Yoon
2024	—	`conf`	A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Bodhisatta Pramanik, Mingyu Woo
2024	J	`jnl`	A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Trans. Design Autom. Electr. Syst. Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
2024	J	`jnl`	An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. ACM Trans. Design Autom. Electr. Syst. Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
2024	J	`jnl`	DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators. CoRR Andrew B. Kahng, Zhiang Wang
2024	J	`jnl`	Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang
2024	A	`conf`	Improvement of Mixed Track - Height Standard-Cell Placement. DATE Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon
2024	J	`jnl`	K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang
2024	A*	`conf`	NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem. AAAI Andrew B. Kahng, Robert R. Nerem, Yusu Wang, Chien-Yi Yang
2024	Misc	`conf`	OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. VTS Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu
2024	A*	`conf`	PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. DAC Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, SeongHyeon Park, Bodhisatta Pramanik
2024	J	`jnl`	PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon
2024	—	`conf`	Panel Statement: EDA Needs at Advanced Technology Nodes. ISPD Andrew B. Kahng
2024	A	`conf`	Placement Tomography-Based Routing Blockage Generation for DRV Hotspot Mitigation. ICCAD Andrew B. Kahng, Sayak Kundu, Dooseok Yoon
2024	—	`conf`	SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization. ISQED Joong-Won Jeon, Andrew B. Kahng, Jaehyun Kang, Jaehwan Kim, Mingyu Woo
2024	—	`conf`	Scalable Flip-Flop Clustering Using Divide and Conquer For Capacitated K-Means. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Sayak Kundu, Shreyas Thumathy
2024	—	`conf`	Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design. ISPD Andrew B. Kahng
2024	A	`conf`	Strengthening the Foundations for IC Physical Design and ML EDA Research. ICCAD Vidya A. Chhabria, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Bing-Yue Wu, Dooseok Yoon
2024	J	`jnl`	The TILOS AI Institute: Integrating optimization and AI for chip design, networks, and robotics. AI Mag. Andrew B. Kahng, Arya Mazumdar, Jodi Reeves, Yusu Wang
2023	J	`jnl`	A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. CoRR Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
2023	—	`conf`	An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing. ISQED Andrew B. Kahng, Shreyas Thumathy, Mingyu Woo
2023	A	`conf`	An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design. ICCAD Ismail Bustany, Grigor Gasparyan, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang
2023	J	`jnl`	An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. CoRR Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
2023	—	`conf`	Assessment of Reinforcement Learning for Macro Placement. ISPD Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang
2023	J	`jnl`	Assessment of Reinforcement Learning for Macro Placement. CoRR Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang
2023	J	`jnl`	DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. ACM Trans. Design Autom. Electr. Syst. Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa
2023	—	`conf`	Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration. SLIP Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon
2023	J	`jnl`	Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks. CoRR Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang
2023	A	`conf`	Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research. ICCAD Jinwook Jung, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Dooseok Yoon
2023	A	`conf`	Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. ICCAD Jiang Hu, Andrew B. Kahng
2023	J	`jnl`	K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement. CoRR Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang
2023	J	`jnl`	Machine Learning for CAD/EDA: The Road Ahead. IEEE Des. Test Andrew B. Kahng
2023	J	`jnl`	NN-Steiner: A Mixed Neural-algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem. CoRR Andrew B. Kahng, Robert R. Nerem, Yusu Wang, Chien-Yi Yang
2023	J	`jnl`	PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement. CoRR Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon
2023	J	`jnl`	Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations. CoRR Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
2023	—	`conf`	The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results. MLCAD Ismail Bustany, Grigor Gasparyan, Amit Gupta, Andrew B. Kahng, Meghraj Kalase, Wuxi Li, Bodhisatta Pramanik
2022	A	`conf`	A Mixed Open-Source and Proprietary EDA Commons for Education and Prototyping. ICCAD Andrew B. Kahng
2022	—	`conf`	AI/ML, Optimization and EDA in the TILOS AI Research Institute. ACM Great Lakes Symposium on VLSI Andrew B. Kahng
2022	—	`conf`	From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. MLCAD Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
2022	A	`conf`	IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA. ICCAD Jinwook Jung, Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang
2022	J	`jnl`	In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Jian Kuang, Wen-Hao Liu, Bangqi Xu
2022	—	`conf`	Leveling Up: A Trajectory of OpenROAD, TILOS and Beyond. ISPD Andrew B. Kahng
2022	J	`jnl`	PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo
2022	—	`conf`	Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms. MLCAD Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
2022	—	`conf`	RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement. ISPD Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang
2022	J	`jnl`	RosettaStone: Connecting the Past, Present, and Future of Physical Design Research. IEEE Des. Test Andrew B. Kahng, Minsoo Kim, Seungwon Kim, Mingyu Woo
2022	A	`conf`	SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement. ICCAD Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang
2022	J	`jnl`	TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Lutong Wang, Bangqi Xu
2021	—	`conf`	Advancing Placement. ISPD Andrew B. Kahng
2021	C	`conf`	CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. ICCD Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo
2021	A	`conf`	DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo
2021	J	`jnl`	Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Bangqi Xu
2021	A	`conf`	METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session Paper. ICCAD Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan
2021	J	`jnl`	TritonRoute: The Open-Source Detailed Router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Lutong Wang, Bangqi Xu
2021	A	`conf`	VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. ICCAD Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng
2020	J	`jnl`	Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Aditya Narayan, Vaishnav Srinivas
2020	A	`conf`	DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
2020	J	`jnl`	Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
2020	—	`conf`	MLCAD Today and Tomorrow: Learning, Optimization and Scaling. MLCAD Andrew B. Kahng
2020	J	`jnl`	On the superiority of modularity-based clustering for determining placement-relevant clusters. Integr. Mateus Fogaça, Andrew B. Kahng, Eder Monteiro, Ricardo Reis, Lutong Wang, Mingyu Woo
2020	C	`conf`	Open-Source EDA: If We Build It, Who Will Come? VLSI-SOC Andrew B. Kahng
2020	J	`jnl`	Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kwangsoo Han, Andrew B. Kahng, Jiajia Li
2020	—	`conf`	Optimal bounded-skew steiner trees to minimize maximum SLIP Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez
2020	—	`conf`	Revisiting inherent noise floors for interconnect prediction. SLIP Tuck-Boon Chan, Andrew B. Kahng, Mingyu Woo
2020	—	`ed.`	SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020 SLIP Andrew B. Kahng
2020	—	`conf`	Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. ASP-DAC Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu
2020	A*	`conf`	The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing. DAC Andrew B. Kahng, Lutong Wang, Bangqi Xu
2020	Misc	`conf`	Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update. VLSID Abdelrahman Hosny, Andrew B. Kahng
2019	A	`conf`	"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design. DATE Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul, Shangyuan Tong
2019	A	`conf`	DATC RDF-2019: Towards a Complete Academic Reference Design Flow. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
2019	A	`conf`	Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI. DATE Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang, Chutong Yang
2019	—	`conf`	Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI. ASP-DAC Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang
2019	J	`jnl`	Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Changho Han, Andrew B. Kahng, Lutong Wang, Bangqi Xu
2019	J	`jnl`	Enhancing sensitivity-based power reduction for an industry IC design context. Integr. Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
2019	—	`conf`	Finding placement-relevant clusters with fast modularity-based clustering. ASP-DAC Mateus Fogaça, Andrew B. Kahng, Ricardo Reis, Lutong Wang
2019	A	`conf`	IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. ICCAD Chia-Tung Ho, Andrew B. Kahng
2019	—	`conf`	Learning-based prediction of package power delivery network quality. ASP-DAC Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu
2019	A	`conf`	Looking Into the Mirror of Open Source: Invited Paper. ICCAD Andrew B. Kahng
2019	A	`conf`	Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology. DATE Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu
2019	J	`jnl`	RePlAce: Advancing Solution Quality and Routability Validation in Global Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang
2019	A*	`conf`	Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu
2018	A	`conf`	A cross-layer methodology for design and optimization of networks in 2.5D systems. ICCAD Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Vaishnav Srinivas
2018	—	`conf`	A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. SLIP@DAC Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky
2018	J	`jnl`	Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sorin Dobre, Andrew B. Kahng, Jiajia Li
2018	—	`conf`	Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout. ISPD Andrew B. Kahng
2018	A	`conf`	Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. DATE Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful A. Mojumder, Tiansheng Zhang
2018	—	`conf`	Machine Learning Applications in Physical Design: Recent Results and Directions. ISPD Andrew B. Kahng
2018	—	`conf`	New directions for learning-based IC design tools and methodologies. ASP-DAC Andrew B. Kahng
2018	J	`jnl`	PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li
2018	—	`ch.`	Practical Approximations of Steiner Trees in Uniform Orientation Metrics. Handbook of Approximation Algorithms and Metaheuristics (1) Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
2018	—	`conf`	Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
2018	A*	`conf`	Reducing time and effort in IC implementation: a roadmap of challenges and solutions. DAC Andrew B. Kahng
2018	J	`jnl`	Silicon Photonics for Computing Systems. ACM J. Emerg. Technol. Comput. Syst. Jiang Xu, Yuichi Nakamura, Andrew B. Kahng
2018	—	`conf`	Theory and Algorithms of Physical Design. ISPD Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng
2018	A	`conf`	TritonRoute: an initial detailed router for advanced VLSI technologies. ICCAD Andrew B. Kahng, Lutong Wang, Bangqi Xu
2018	C	`conf`	Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis. ICCD Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul
2018	—	`conf`	Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics. ISPD Andrew B. Kahng, Christopher Moyes, Sriram Venkatesh, Lutong Wang
2017	J	`jnl`	Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José L. Abellán, Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Cristian Morales, John Recchio, Vaishnav Srinivas, Tiansheng Zhang
2017	J	`jnl`	Benchmarking of Mask Fracturing Heuristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng
2017	J	`jnl`	CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
2017	—	`conf`	Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
2017	J	`jnl`	Guest Editorial: Alternative Computing and Machine Learning for Internet of Things. IEEE Trans. Very Large Scale Integr. Syst. Farshad Firouzi, Bahar J. Farahani, Andrew B. Kahng, Jan M. Rabaey, Natasha Balac
2017	C	`conf`	ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning. ICCD Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng
2017	J	`jnl`	Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
2017	J	`jnl`	MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2017	J	`jnl`	Optimal Scheduling and Allocation for IC Design Management and Cost Reduction. ACM Trans. Design Autom. Electr. Syst. Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath
2017	A	`conf`	Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. ICCAD Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu
2017	—	`conf`	Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. ISQED Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang
2017	J	`jnl`	Revisiting 3DIC benefit with multiple tiers. Integr. Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li
2017	—	`conf`	Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. ISPD Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena
2017	J	`jnl`	Trading Accuracy for Energy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
2017	A*	`conf`	Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2016	C	`conf`	BEOL stack-aware routability prediction from placement using data mining techniques. ICCD Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi
2016	A*	`conf`	Comprehensive optimization of scan chain timing during late-stage IC implementation. DAC Kun Young Chung, Andrew B. Kahng, Jiajia Li
2016	A	`conf`	Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems. DATE Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang
2016	—	`conf`	Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. ASP-DAC Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo
2016	A	`conf`	Improved flop tray-based design implementation for power reduction. ICCAD Andrew B. Kahng, Jiajia Li, Lutong Wang
2016	A	`conf`	Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. DATE Kwangsoo Han, Andrew B. Kahng, Jiajia Li
2016	—	`conf`	Learning-based prediction of embedded memory timing failures during initial floorplan design. ASP-DAC Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath
2016	A	`conf`	Measuring progress and value of IC implementation technology. ICCAD Andrew B. Kahng, Hyein Lee, Jiajia Li
2016	—	`conf`	Revisiting 3DIC Benefit with Multiple Tiers. SLIP Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li
2015	A*	`conf`	3DIC benefit estimation and implementation guidance from 2DIC implementation. DAC Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi
2015	A*	`conf`	A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee
2015	J	`jnl`	An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez
2015	J	`jnl`	Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. ACM J. Emerg. Technol. Comput. Syst. Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang
2015	J	`jnl`	CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2015	—	`conf`	Clock clustering and IO optimization for 3D integration. SLIP Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas
2015	—	`conf`	Crosstalk-aware signal probability-based dynamic statistical timing analysis. ISQED Yao Chen, Andrew B. Kahng, Bao Liu, Wenjun Wang
2015	A*	`conf`	Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. DAC Kwangsoo Han, Andrew B. Kahng, Hyein Lee
2015	A	`conf`	Evolving EDA Beyond its E-Roots: An Overview. ICCAD Andrew B. Kahng, Farinaz Koushanfar
2015	A	`conf`	Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. ICCAD Sorin Dobre, Andrew B. Kahng, Jiajia Li
2015	A	`conf`	Modeling the future of semiconductors (and test!). ITC Andrew B. Kahng
2015	—	`conf`	Multi-product floorplan and uncore design framework for chip multiprocessors. SLIP Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Ümit Y. Ogras, Kambiz Samadi
2015	A*	`conf`	New game, new goal posts: a recent history of timing closure. DAC Andrew B. Kahng
2015	J	`jnl`	ORION3.0: A Comprehensive NoC Router Estimation Tool. IEEE Embed. Syst. Lett. Andrew B. Kahng, Bill Lin, Siddhartha Nath
2015	J	`jnl`	Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park
2015	A	`conf`	Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. ICCAD Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
2015	—	`conf`	SI for free: machine learning of interconnect coupling delay and transition effects. SLIP Andrew B. Kahng, Mulong Luo, Siddhartha Nath
2015	A	`conf`	Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. ICCAD Kwangsoo Han, Andrew B. Kahng, Hyein Lee
2015	A	`conf`	Toward Metrics of Design Automation Research Impact. ICCAD Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins
2014	A	`conf`	A deep learning methodology to proliferate golden signoff timing. DATE Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan
2014	—	`conf`	A new methodology for reduced cost of resilience. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Seokhyeong Kang, Jiajia Li
2014	A	`conf`	Benchmarking of mask fracturing heuristics. ICCAD Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria
2014	A	`conf`	Co-optimization of memory BIST grouping, test scheduling, and logic placement. DATE Andrew B. Kahng, Ilgweon Kang
2014	—	`conf`	Horizontal benchmark extension for improved assessment of physical CAD research. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Hyein Lee, Jiajia Li
2014	C	`conf`	ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. ICCD Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath
2014	C	`conf`	Improved signoff methodology with tightened BEOL corners. ICCD Tuck-Boon Chan, Sorin Dobre, Andrew B. Kahng
2014	—	`conf`	Methodology for electromigration signoff in the presence of adaptive voltage scaling. SLIP Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath
2014	—	`conf`	Minimum implant area-aware gate sizing and placement. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Hyein Lee
2014	A	`conf`	Mission profile aware IC design - A case study. DATE Goeran Jerke, Andrew B. Kahng
2014	—	`conf`	NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. ISQED Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
2014	—	`conf`	OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath
2014	J	`jnl`	On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng
2014	—	`conf`	Optimal reliability-constrained overdrive frequency selection in multicore systems. ISQED Andrew B. Kahng, Siddhartha Nath
2014	J	`jnl`	Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors. IEEE Trans. Very Large Scale Integr. Syst. Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai
2014	C	`conf`	The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. ICCD Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto
2014	—	`conf`	Timing margin recovery with flexible flip-flop timing model. ISQED Andrew B. Kahng, Hyein Lee
2014	—	`conf`	Toward Holistic Modeling, Margining and Tolerance of IC Variability. ISVLSI Andrew B. Kahng
2013	A	`conf`	Active-mode leakage reduction with data-retained power gating. DATE Andrew B. Kahng, Seokhyeong Kang, Bongil Park
2013	A	`conf`	Enhanced metamodeling techniques for high-dimensional IC design estimation problems. DATE Andrew B. Kahng, Bill Lin, Siddhartha Nath
2013	J	`jnl`	Enhancing the Efficiency of Energy-Constrained DVFS Designs. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013	—	`conf`	High-dimensional metamodeling for prediction of clock tree synthesis outcomes. SLIP Andrew B. Kahng, Bill Lin, Siddhartha Nath
2013	A	`conf`	High-performance gate sizing with a signoff timer. ICCAD Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar
2013	A	`conf`	Impact of adaptive voltage scaling on aging-aware signoff. DATE Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng
2013	A	`conf`	Incremental multiple-scan chain ordering for ECO flip-flop insertion. ICCAD Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath
2013	—	`conf`	Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani
2013	J	`jnl`	Many-Core Token-Based Adaptive Power Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong
2013	—	`conf`	On potential design impacts of electromigration awareness. ASP-DAC Andrew B. Kahng, Siddhartha Nath, Tajana Rosing
2013	—	`conf`	Optimization of overdrive signoff. ASP-DAC Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath
2013	—	`conf`	Reliability-constrained die stacking order in 3DICs under manufacturing variability. ISQED Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
2013	A*	`conf`	Smart non-default routing for clock power reduction. DAC Andrew B. Kahng, Seokhyeong Kang, Hyein Lee
2013	C	`conf`	Statistical analysis and modeling for error composition in approximate computation circuits. ICCD Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013	A*	`conf`	The ITRS design technology and system drivers roadmap: process and status. DAC Andrew B. Kahng
2013	—	`conf`	Toward quantifying the IC design value of interconnect technology improvements. SLIP Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
2012	A*	`conf`	Accuracy-configurable adder for approximate arithmetic designs. DAC Andrew B. Kahng, Seokhyeong Kang
2012	A	`conf`	CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2012	—	`conf`	Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD Andrew B. Kahng, Seokhyeong Kang
2012	—	`conf`	DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. ISQED Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai
2012	A*	`conf`	Explicit modeling of control and data for improved NoC router estimation. DAC Andrew B. Kahng, Bill Lin, Siddhartha Nath
2012	—	`conf`	Improved path clustering for adaptive path-delay testing. ISQED Tuck-Boon Chan, Andrew B. Kahng
2012	—	`conf`	Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. ISPD Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng
2012	A	`conf`	MAPG: Memory access power gating. DATE Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong
2012	J	`jnl`	ORION 2.0: A Power-Area Simulator for Interconnection Networks. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi
2012	J	`jnl`	Predicting the future of information technology and society [The Road Ahead]. IEEE Des. Test Comput. Andrew B. Kahng
2012	J	`jnl`	Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2012	A	`conf`	Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov
2012	A	`conf`	TAP: token-based adaptive power gating. ISLPED Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong
2012	A	`conf`	Tunable sensors for process-aware voltage scaling. ICCAD Tuck-Boon Chan, Andrew B. Kahng
2011	J	`jnl`	Big Chips. IEEE Micro Andrew B. Kahng, Vijayalakshmi Srinivasan
2011	J	`jnl`	Design for manufacturability: Then and now. IEEE Des. Test Comput. Andrew B. Kahng
2011	—	`conf`	Mobile system considerations for SDRAM interface trends. SLIP Andrew B. Kahng, Vaishnav Srinivas
2011	—	`conf`	More realistic power grid verification based on hierarchical current and power constraints. ISPD Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong
2011	J	`jnl`	Product Futures. IEEE Des. Test Comput. Andrew B. Kahng
2011	J	`jnl`	Roadmapping Power. IEEE Des. Test Comput. Andrew B. Kahng
2011	J	`jnl`	Roads not taken. IEEE Des. Test Comput. Andrew B. Kahng
2011	—	`conf`	Stability and scalability in global routing. SLIP Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu
2011	J	`jnl`	The Future of Signoff. IEEE Des. Test Comput. Andrew B. Kahng
2011	—	`conf`	Toward PDN resource estimation: A law of general power density. SLIP Kwangok Jeong, Andrew B. Kahng
2011	—	`book`	VLSI Physical Design - From Graph Partitioning to Timing Closure. Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
2010	J	`jnl`	Accurate Machine-Learning-Based On-Chip Router Modeling. IEEE Embed. Syst. Lett. Kwangok Jeong, Andrew B. Kahng, Binshan Lin, Kambiz Samadi
2010	J	`jnl`	Accurate Predictive Interconnect Modeling for System-Level Design. IEEE Trans. Very Large Scale Integr. Syst. Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma
2010	—	`conf`	Assessing chip-level impact of double patterning lithography. ISQED Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu
2010	A*	`conf`	Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	J	`jnl`	Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2010	A	`conf`	Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations. ICCAD Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam
2010	A*	`conf`	Eyecharts: constructive benchmarking of gate sizing heuristics. DAC Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma
2010	—	`conf`	Improved on-chip router analytical power and area modeling. ASP-DAC Andrew B. Kahng, Bill Lin, Kambiz Samadi
2010	J	`jnl`	Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
2010	—	`conf`	Methodology from chaos in IC implementation. ISQED Kwangok Jeong, Andrew B. Kahng
2010	A*	`conf`	Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	J	`jnl`	Scaling: More than Moore's law. IEEE Des. Test Comput. Andrew B. Kahng
2010	—	`conf`	Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	J	`jnl`	Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
2010	—	`conf`	Toward effective utilization of timing exceptions in design optimization. ISQED Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
2010	A*	`conf`	Trace-driven optimization of networks-on-chip configurations. DAC Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam
2010	J	`jnl`	When is 3D 2B? IEEE Des. Test Comput. Andrew B. Kahng
2010	—	`conf`	Worst-case performance prediction under supply voltage and temperature variation. SLIP Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani
2009	—	`conf`	Is overlay error more important than interconnect variations in double patterning? SLIP Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu
2009	J	`jnl`	Lens aberration aware placement for timing yield. ACM Trans. Design Autom. Electr. Syst. Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
2009	A	`conf`	ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. DATE Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi
2009	—	`conf`	Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED Kwangok Jeong, Andrew B. Kahng, Hailong Yao
2009	C	`conf`	Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. DSD Ayse K. Coskun, Andrew B. Kahng, Tajana Simunic Rosing
2009	—	`conf`	Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. ASP-DAC Kwangok Jeong, Andrew B. Kahng
2009	A	`conf`	Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. ICCAD Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
2008	A*	`conf`	Bounded-lifetime integrated circuits. DAC Puneet Gupta, Andrew B. Kahng
2008	—	`ch.`	CMP Fill Synthesis. Handbook of Algorithms for Physical Design Automation Andrew B. Kahng, Kambiz Samadi
2008	J	`jnl`	CMP Fill Synthesis: A Survey of Recent Studies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Kambiz Samadi
2008	J	`jnl`	Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu
2008	A*	`conf`	DFM in practice: hit or hype? DAC Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh
2008	J	`jnl`	Defocus-Aware Leakage Estimation and Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma
2008	A*	`conf`	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2008	J	`jnl`	Fast Dual-Graph-Based Hotspot Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Chul-Hong Park, Xu Xu
2008	—	`conf`	How to get real mad. ISPD Andrew B. Kahng
2008	—	`conf`	Interconnect modeling for improved system-level design optimization. ASP-DAC Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma
2008	—	`conf`	Investigation of diffusion rounding for post-lithography analysis. ASP-DAC Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
2008	A	`conf`	Layout decomposition for double patterning lithography. ICCAD Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
2008	—	`conf`	Quantified Impacts of Guardband Reduction on Design Process Outcomes. ISQED Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi
2007	—	`conf`	A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. ISQED Andrew B. Kahng, Rasit Onur Topaloglu
2007	—	`conf`	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman
2007	—	`ch.`	APlace: A High Quality, Large-Scale Analytical Placer. Modern Circuit Placement Andrew B. Kahng, Sherief Reda, Qinke Wang
2007	C	`conf`	Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu
2007	J	`jnl`	Bright-Field AAPSM Conflict Detection and Correction CoRR Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
2007	A	`conf`	Design challenges at 65nm and beyond. DATE Andrew B. Kahng
2007	J	`jnl`	Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
2007	A	`conf`	Detailed placement for leakage reduction using systematic through-pitch variation. ISLPED Andrew B. Kahng, Swamy Muddu, Puneet Sharma
2007	J	`jnl`	Enhanced Design Flow and Optimizations for Multiproject Wafers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Ion I. Mandoiu, Xu Xu, Alexander Zelikovsky
2007	A	`conf`	Exploiting STI stress for performance. ICCAD Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu
2007	J	`jnl`	Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
2007	—	`conf`	Key directions and a roadmap for electrical design for manufacturability. ESSCIRC Andrew B. Kahng
2007	A*	`conf`	Line-End Shortening is Not Always a Failure. DAC Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
2007	—	`ch.`	Multicommodity Flow Algorithms for Buffered Global Routing. Handbook of Approximation Algorithms and Metaheuristics Ion I. Mandoiu, Andrew B. Kahng, Christoph Albrecht, Alexander Zelikovsky
2007	—	`conf`	On-Line Adjustable Buffering for Runtime Power Reduction. ISQED Andrew B. Kahng, Sherief Reda, Puneet Sharma
2007	—	`ch.`	Practical Approximations of Steiner Trees in Uniform Orientation Metrics. Handbook of Approximation Algorithms and Metaheuristics Ion I. Mandoiu, Andrew B. Kahng, Alexander Zelikovsky
2007	J	`jnl`	Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. IEEE Des. Test Comput. Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias
2007	J	`jnl`	Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
2007	J	`jnl`	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2007	J	`jnl`	Statistical Timing Analysis in the Presence of Signal-Integrity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Bao Liu, Xu Xu
2007	J	`jnl`	Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Bao Liu, Qinke Wang
2006	J	`jnl`	A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
2006	—	`conf`	A faster implementation of APlace. ISPD Andrew B. Kahng, Qinke Wang
2006	—	`conf`	A tale of two nets: studies of wirelength progression in physical design. SLIP Andrew B. Kahng, Sherief Reda
2006	A*	`conf`	CAD challenges for leading-edge multimedia designs. DAC Andrew B. Kahng
2006	J	`jnl`	Computer-Aided Optimization of DNA Array Design and Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2006	—	`conf`	Constructing Current-Based Gate Models Based on Existing Timing Library. ISQED Andrew B. Kahng, Bao Liu, Xu Xu
2006	A*	`conf`	DFM: where's the proof of value? DAC Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan
2006	Misc	`conf`	Efficient Design and Analysis of Robust Power Distribution Meshes. VLSI Design Puneet Gupta, Andrew B. Kahng
2006	—	`conf`	Efficient decoupling capacitor planning via convex programming methods. ISPD Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
2006	A	`conf`	Fill for shallow trench isolation CMP. ICCAD Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky
2006	J	`jnl`	Gate-length biasing for runtime-leakage control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
2006	—	`conf`	Generation of design guarantees for interconnect matching. SLIP Andrew B. Kahng, Rasit Onur Topaloglu
2006	—	`conf`	Impact of Gate-Length Biasing on Threshold-Voltage Selection. ISQED Andrew B. Kahng, Swamy Muddu, Puneet Sharma
2006	C	`conf`	Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. ICCD Rasit Onur Topaloglu, Andrew B. Kahng
2006	A	`conf`	Lens aberration aware timing-driven placement. DATE Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
2006	J	`jnl`	New and improved BIST diagnosis methods from combinatorial Group testing theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sherief Reda
2006	—	`conf`	SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
2006	A*	`conf`	Standard cell library optimization for leakage reduction. DAC Saumil Shah, Puneet Gupta, Andrew B. Kahng
2006	—	`conf`	Statistical crosstalk aggressor alignment aware interconnect delay calculation. SLIP Andrew B. Kahng, Bao Liu, Xu Xu
2006	—	`conf`	Statistical gate delay calculation with crosstalk alignment consideration. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Bao Liu, Xu Xu
2006	—	`conf`	Study of Floating Fill Impact on Interconnect Capacitance. ISQED Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
2006	A*	`conf`	Timing-driven Steiner trees are (practically) free. DAC Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
2006	J	`jnl`	Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu
2006	J	`jnl`	Wirelength minimization for min-cut placements via placement feedback. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sherief Reda
2006	J	`jnl`	Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sherief Reda
2005	—	`conf`	A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ISQED Puneet Gupta, Andrew B. Kahng, Puneet Sharma
2005	—	`conf`	A semi-persistent clustering technique for VLSI circuit placement. ISPD Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
2005	—	`conf`	APlace: a general analytic placement framework. ISPD Andrew B. Kahng, Sherief Reda, Qinke Wang
2005	A*	`conf`	Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
2005	A	`conf`	Architecture and details of a high quality, large-scale analytical placer. ICCAD Andrew B. Kahng, Sherief Reda, Qinke Wang
2005	A	`conf`	Bright-Field AAPSM Conflict Detection and Correction. DATE Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
2005	J	`jnl`	Compressible area fill synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
2005	J	`jnl`	DAC Highlights. IEEE Des. Test Comput. Andrew B. Kahng, Grant Martin
2005	A	`conf`	Defocus-aware leakage estimation and control. ISLPED Andrew B. Kahng, Swamy Muddu, Puneet Sharma
2005	—	`conf`	Detailed placement for improved depth of focus and CD control. ASP-DAC Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
2005	—	`conf`	Evaluation of placer suboptimality via zero-change netlist transformations. ISPD Andrew B. Kahng, Sherief Reda
2005	A	`conf`	Fast and efficient phase conflict detection and correction in standard-cell layouts. ICCAD Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu
2005	J	`jnl`	Implementation and extensibility of an analytic placer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Qinke Wang
2005	A	`conf`	Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ICCAD Andrew B. Kahng, Sherief Reda
2005	J	`jnl`	Layout-aware scan chain synthesis for improved path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
2005	J	`jnl`	Multicommodity Flow Algorithms for Buffered Global Routing CoRR Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
2005	—	`conf`	Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
2005	—	`conf`	Performance Driven OPC for Mask Cost Reduction. ISQED Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
2005	A*	`conf`	Power-aware placement. DAC Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang
2005	A*	`ed.`	Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005 DAC William H. Joyner Jr., Grant Martin, Andrew B. Kahng
2005	J	`jnl`	Routing-aware scan chain ordering. ACM Trans. Design Autom. Electr. Syst. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
2005	—	`conf`	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ISPD Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2005	C	`conf`	Supply Voltage Degradation Aware Analytical Placement. ICCD Andrew B. Kahng, Bao Liu, Qinke Wang
2005	J	`jnl`	The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2004	J	`jnl`	2003 Technology Roadmap for Semiconductors. Computer Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian
2004	A	`conf`	An analytic placer for mixed-size placement and timing-driven placement. ICCAD Andrew B. Kahng, Qinke Wang
2004	A	`conf`	Boosting: Min-Cut Placement with Improved Signal Delay. DATE Andrew B. Kahng, Igor L. Markov, Sherief Reda
2004	—	`conf`	Combinatorial group testing methods for the BIST diagnosis problem. ASP-DAC Andrew B. Kahng, Sherief Reda
2004	J	`jnl`	Effective iterative techniques for fingerprinting design IP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
2004	—	`conf`	Evaluation of the new OASIS format for layout fill compression. ICECS Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
2004	J	`jnl`	Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice. IEEE Des. Test Comput. Dwight D. Hill, Andrew B. Kahng
2004	—	`conf`	Implementation and extensibility of an analytic placer. ISPD Andrew B. Kahng, Qinke Wang
2004	—	`conf`	Investigation of performance metrics for interconnect stack architectures. SLIP Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
2004	J	`jnl`	Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Xu Xu
2004	—	`conf`	Manufacturability . ISQED Andrew B. Kahng
2004	J	`jnl`	Match twice and stitch: a new TSP tour construction heuristic. Oper. Res. Lett. Andrew B. Kahng, Sherief Reda
2004	—	`conf`	Multi-project reticle floorplanning and wafer dicing. ISPD Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky
2004	J	`jnl`	Nontree routing for reliability and yield improvement [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
2004	—	`conf`	On legalization of row-based placements. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Igor L. Markov, Sherief Reda
2004	—	`conf`	Optimal planning for mesh-based power distribution. ASP-DAC Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
2004	A*	`conf`	Placement feedback: a concept and method for better min-cut placements. DAC Andrew B. Kahng, Sherief Reda
2004	A*	`ed.`	Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 DAC Sharad Malik, Limor Fix, Andrew B. Kahng
2004	A*	`conf`	Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. DAC Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier
2004	J	`jnl`	Scalable Heuristics for Design of DNA Probe Arrays. J. Comput. Biol. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
2004	A*	`conf`	Selective gate-length biasing for cost-effective runtime leakage control. DAC Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
2004	A*	`conf`	Toward a methodology for manufacturability-driven design rule exploration. DAC Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
2004	Misc	`conf`	Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. VLSI Design Puneet Gupta, Andrew B. Kahng
2003	A	`conf`	A Novel Metric for Interconnect Architecture Performance. DATE Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu
2003	—	`conf`	A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. ISQED Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
2003	A*	`conf`	A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
2003	—	`conf`	Accurate pseudo-constructive wirelength and congestion estimation. SLIP Andrew B. Kahng, Xu Xu
2003	A*	`conf`	An algebraic multigrid solver for analytical placement with layout based clustering. DAC Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
2003	A	`conf`	Area Fill Generation With Inherent Data Volume Reduction. DATE Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
2003	J	`jnl`	Bringing down NRE. IEEE Des. Test Comput. Andrew B. Kahng
2003	C	`conf`	Design Flow Enhancements for DNA Arrays. ICCD Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2003	B	`conf`	Engineering a scalable placement heuristic for DNA probe arrays. RECOMB Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
2003	J	`jnl`	Error Tolerance. IEEE Des. Test Comput. Andrew B. Kahng
2003	—	`conf`	Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
2003	A	`conf`	Evaluation of Placement Techniques for DNA Probe Array Layout. ICCAD Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2003	J	`jnl`	Hierarchical whitespace allocation in top-down placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2003	—	`conf`	Highly scalable algorithms for rectilinear and octilinear Steiner trees. ASP-DAC Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
2003	J	`jnl`	How much variability can designers tolerate? IEEE Des. Test Comput. Andrew B. Kahng
2003	—	`conf`	Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. ISQED Andrew B. Kahng, Igor L. Markov
2003	J	`jnl`	Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. Very Large Scale Integr. Syst. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
2003	A	`conf`	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. ICCAD Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
2003	—	`conf`	Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. ISPD Andrew B. Kahng, Xu Xu
2003	A	`conf`	Manufacturing-Aware Physical Design. ICCAD Puneet Gupta, Andrew B. Kahng
2003	J	`jnl`	Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
2003	A*	`conf`	Nanometer design: place your bets. DAC Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
2003	J	`jnl`	On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
2003	A*	`conf`	Performance-impact limited area fill synthesis. DAC Yu Chen, Puneet Gupta, Andrew B. Kahng
2003	—	`conf`	Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. ISVLSI Andrew B. Kahng, Bao Liu
2003	—	`conf`	Quantifying Error in Dynamic Power Estimation of CMOS Circuits. ISQED Puneet Gupta, Andrew B. Kahng
2003	—	`conf`	Research directions for coevolution of rules and routers. ISPD Andrew B. Kahng
2003	—	`conf`	Routing-aware scan chain ordering. ASP-DAC Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
2003	A	`conf`	The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2002	J	`jnl`	2001 Technology Roadmap for Semiconductors. Computer Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian
2002	—	`conf`	A New Design Cost Model for the 2001 ITRS (invited). ISQED Andrew B. Kahng, Gary Smith
2002	—	`conf`	A roadmap and vision for physical design. ISPD Andrew B. Kahng
2002	J	`jnl`	Area fill synthesis for uniform layout density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
2002	J	`jnl`	Asymmetric Binary Covering Codes. J. Comb. Theory A Joshua N. Cooper, Robert B. Ellis, Andrew B. Kahng
2002	—	`conf`	Auctions with Buyer Preferences. Information Systems: The e-Business Challenge C. Bandela, Yu Chen, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
2002	C	`conf`	Border Length Minimization in DNA Array Design. WABI Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
2002	—	`conf`	Closing the smoothness and uniformity gap in area fill synthesis. ISPD Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
2002	—	`conf`	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ASP-DAC/VLSI Design Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
2002	—	`conf`	Measurement of Inherent Noise in EDA Tools. ISQED Andrew B. Kahng, Stefanus Mantik
2002	—	`conf`	Min-max placement for large-scale timing optimization. ISPD Andrew B. Kahng, Stefanus Mantik, Igor L. Markov
2002	A	`conf`	Non-tree routing for reliability and yield improvement. ICCAD Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
2002	J	`jnl`	Provably good global buffering by generalized multiterminalmulticommodity flow approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2002	J	`jnl`	The Road Ahead: The significance of packaging. IEEE Des. Test Comput. Andrew B. Kahng
2002	A*	`conf`	Tools or users: which is the bigger bottleneck? DAC Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven
2002	J	`jnl`	Toward better wireload models in the presence of obstacles. IEEE Trans. Very Large Scale Integr. Syst. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
2002	J	`jnl`	Variability. IEEE Des. Test Comput. Andrew B. Kahng
2001	—	`conf`	A System for Automatic Recording and Prediction of Design Quality Metrics. ISQED Andrew B. Kahng, Stefanus Mantik
2001	—	`conf`	Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
2001	—	`conf`	Buffered Steiner trees for difficult instances. ISPD Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
2001	J	`jnl`	Constraint-based watermarking techniques for design IP protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
2001	—	`conf`	Design Metrics to Achieve Design Quality. ISQED Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats
2001	—	`conf`	Design technology productivity in the DSM era (invited talk). ASP-DAC Andrew B. Kahng
2001	J	`jnl`	Guest Editor's Introduction: Roadmaps and Visions for Design and Test. IEEE Des. Test Comput. William H. Joyner Jr., Andrew B. Kahng
2001	—	`conf`	Hierarchical dummy fill for process uniformity. ASP-DAC Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
2001	—	`conf`	Interconnect implications of growth-based structural models for VLSI circuits. SLIP Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
2001	J	`jnl`	Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
2001	A	`conf`	Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
2001	—	`conf`	New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. ASP-DAC Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky
2001	—	`conf`	Noise Model for Multiple Segmented Coupled RC Interconnects. ISQED Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
2001	—	`conf`	On the relevance of wire load models. SLIP Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik
2001	A*	`conf`	Panel: Is Nanometer Design Under Control? DAC Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
2001	B	`conf`	Practical Approximation Algorithms for Separable Packing Linear Programs. WADS Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2001	—	`conf`	Provably good global buffering by multi-terminal multicommodity flow approximation. ASP-DAC Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2001	J	`jnl`	Toward accurate models of achievable routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
2001	—	`conf`	Toward better wireload models in the presence of obstacles. ASP-DAC Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
2000	—	`conf`	Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng
2000	A*	`conf`	Can recursive bisection alone produce routable placements? DAC Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000	—	`conf`	Classical floorplanning harmful? ISPD Andrew B. Kahng
2000	J	`jnl`	Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. ACM J. Exp. Algorithmics Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000	A*	`conf`	EDA meets.COM (panel session): how E-services will change the EDA business model. DAC Jennifer Smith, Tom Quan, Andrew B. Kahng
2000	A	`conf`	Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
2000	A*	`conf`	GTX: the MARCO GSRC technology extrapolation system. DAC Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
2000	J	`jnl`	Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000	—	`conf`	Improved algorithms for hypergraph bipartitioning. ASP-DAC Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000	J	`jnl`	Iterative Partitioning with Varying Node Weights. VLSI Design Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000	A*	`conf`	METRICS: a system architecture for design process optimization. DAC Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges
2000	—	`conf`	Monte-Carlo algorithms for layout density control. ASP-DAC Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
2000	A	`conf`	On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. ICCAD Andrew B. Kahng, Stefanus Mantik
2000	A*	`conf`	On switch factor based analysis of coupled DAC Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
2000	J	`jnl`	Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
2000	J	`jnl`	Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
2000	A*	`conf`	Practical iterated fill synthesis for CMP uniformity. DAC Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
2000	A	`conf`	Provably Good Global Buffering Using an Available Buffer Block Plan. ICCAD Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
2000	—	`conf`	Requirements for models of achievable routing. ISPD Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
2000	—	`conf`	Wiring layer assignments with consistent stage delays. SLIP Andrew B. Kahng, Dirk Stroobandt
1999	J	`jnl`	Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. VLSI Design Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz
1999	A	`conf`	Copy detection for intellectual property protection of VLSI designs. ICCAD Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong
1999	A	`conf`	Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. ALENEX Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999	A*	`conf`	Effective Iterative Techniques for Fingerprinting Design IP. DAC Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
1999	J	`jnl`	Filling algorithms and analyses for layout density control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
1999	—	`conf`	Function Smoothing with Applications to VLSI Layout. ASP-DAC Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
1999	A*	`conf`	Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
1999	A*	`conf`	Hypergraph Partitioning with Fixed Vertices. DAC Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999	Misc	`conf`	Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. VLSI Design Andrew B. Kahng, Sudhakar Muddu
1999	Misc	`conf`	Interconnect Optimization Strategies for High-Performance VLSI Designs. VLSI Design Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
1999	Misc	`conf`	Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. VLSI Design Andrew B. Kahng
1999	—	`conf`	New Multilevel and Hierarchical Algorithms for Layout Density Control. ASP-DAC Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
1999	Misc	`conf`	New and Exact Filling Algorithms for Layout Density Control. VLSI Design Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
1999	J	`jnl`	On wirelength estimations for row-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
1999	—	`conf`	Optimal partitioners and end-case placers for standard-cell layout. ISPD Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999	—	`conf`	Optimal phase conflict removal for layout of dark field alternating phase shifting masks. ISPD Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
1999	—	`conf`	Optimization of Linear Placements for Wirelength Minimization with Free Sites. ASP-DAC Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky
1999	—	`conf`	Partitioning with terminals: a "new" problem and new benchmarks. ISPD Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999	J	`jnl`	Spectral Partitioning with Multiple Eigenvectors. Discret. Appl. Math. Charles J. Alpert, Andrew B. Kahng, So-Zen Yao
1999	A*	`conf`	Subwavelength Lithography and Its Potential Impact on Design and EDA. DAC Andrew B. Kahng, Y. C. Pati
1999	A*	`conf`	Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). DAC Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser
1999	—	`conf`	Subwavelength optical lithography: challenges and impact on physical design. ISPD Andrew B. Kahng, Y. C. Pati
1999	B	`conf`	The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout. WADS Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Alexander Zelikovsky
1999	A	`conf`	The associative-skew clock routing problem. ICCAD Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky
1999	J	`jnl`	Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs. VLSI Design Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
1998	J	`jnl`	Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
1998	J	`jnl`	Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
1998	J	`jnl`	Faster minimization of linear wirelength for global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet
1998	—	`conf`	Filling and slotting: analysis and algorithms. ISPD Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky
1998	—	`conf`	Futures for partitioning in physical design (tutorial). ISPD Andrew B. Kahng
1998	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Majid Sarrafzadeh
1998	J	`jnl`	How to test a tree. Networks Andrew B. Kahng, Gabriel Robins, Elizabeth A. Walkup
1998	A	`conf`	Interconnect Tuning Strategies for High-Performance Ics. DATE Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
1998	J	`jnl`	Multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
1998	—	`conf`	New efficient algorithms for computing effective capacitance. ISPD Andrew B. Kahng, Sudhakar Muddu
1998	—	`conf`	On wirelength estimations for row-based placement. ISPD Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
1998	A*	`conf`	Robust IP Watermarking Methodologies for Physical Design. DAC Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
1998	A*	`conf`	Watermarking Techniques for Intellectual Property Protection. DAC Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
1997	J	`jnl`	An analytical delay model for RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sudhakar Muddu
1997	A*	`conf`	Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
1997	J	`jnl`	Analysis of RC interconnections under ramp input. ACM Trans. Design Autom. Electr. Syst. Andrew B. Kahng, Sudhakar Muddu
1997	J	`jnl`	Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lars W. Hagen, Andrew B. Kahng
1997	J	`jnl`	Cooperative Mobile Robotics: Antecedents and Directions. Auton. Robots Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng
1997	—	`conf`	Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
1997	—	`conf`	Faster minimization of linear wirelength for global placement. ISPD Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan
1997	J	`jnl`	Improved Large-Step Markov Chain Variants for the Symmetric TSP. J. Heuristics Inki Hong, Andrew B. Kahng, Byung Ro Moon
1997	A*	`conf`	More Practical Bounded-Skew Clock Routing. DAC Andrew B. Kahng, Chung-Wen Albert Tsao
1997	A*	`conf`	Multilevel Circuit Partitioning. DAC Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
1997	J	`jnl`	On implementation choices for iterative improvement partitioning algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
1997	—	`conf`	Partitioning-based standard-cell global placement with an exact objective. ISPD Dennis J.-H. Huang, Andrew B. Kahng
1997	J	`jnl`	Practical Bounded-Skew Clock Routing. J. VLSI Signal Process. Andrew B. Kahng, Chung-Wen Albert Tsao
1997	—	`ed.`	Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997 ISPD Andrew B. Kahng, Majid Sarrafzadeh
1996	J	`jnl`	A general framework for vertex orderings with applications to circuit clustering. IEEE Trans. Very Large Scale Integr. Syst. Charles J. Alpert, Andrew B. Kahng
1996	A*	`conf`	Analysis of RC Interconnections Under Ramp Input. DAC Andrew B. Kahng, Sudhakar Muddu
1996	A	`conf`	Analytical delay models for VLSI interconnects under ramp input. ICCAD Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
1996	J	`jnl`	Planar-DME: a single-layer zero-skew clock tree router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Chung-Wen Albert Tsao
1995	A	`conf`	Bounded-skew clock and Steiner routing under Elmore delay. ICCAD Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
1995	—	`conf`	Cooperative mobile robotics: antecedents and directions. IROS (1) Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng, F. Meng
1995	A	`conf`	Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. FPGA Dennis J.-H. Huang, Andrew B. Kahng
1995	J	`jnl`	Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Andrew B. Kahng
1995	J	`jnl`	Near-optimal critical sink routing tree constructions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
1995	J	`jnl`	Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods. INFORMS J. Comput. T. C. Hu, Andrew B. Kahng, Chung-Wen Albert Tsao
1995	—	`conf`	On implementation choices for iterative improvement partitioning algorithms. EURO-DAC Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
1995	A*	`conf`	On the Bounded-Skew Clock and Steiner Routing Problems. DAC Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao
1995	J	`jnl`	Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger
1995	A*	`conf`	Quantified Suboptimality of VLSI Layout Heuristics. DAC Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
1995	J	`jnl`	Recent directions in netlist partitioning: a survey. Integr. Charles J. Alpert, Andrew B. Kahng
1995	—	`conf`	Toward More Powerful Recombinations. ICGA Andrew B. Kahng, Byung Ro Moon
1995	—	`conf`	When clusters meet partitions: new density-based methods for circuit decomposition. ED&TC Dennis J.-H. Huang, Andrew B. Kahng
1994	A	`conf`	A general framework for vertex orderings, with applications to netlist clustering. ICCAD Charles J. Alpert, Andrew B. Kahng
1994	J	`jnl`	A new adaptive multi-start technique for combinatorial global optimizations. Oper. Res. Lett. Kenneth D. Boese, Andrew B. Kahng, Sudhakar Muddu
1994	A*	`conf`	Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. DAC Andrew B. Kahng, Sudhakar Muddu
1994	A	`conf`	Low-cost single-layer clock trees with exact zero Elmore delay skew. ICCAD Andrew B. Kahng, Chung-Wen Albert Tsao
1994	A*	`conf`	Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. DAC Charles J. Alpert, Andrew B. Kahng
1994	J	`jnl`	On the Minimum Density Interconnection Tree Problem. VLSI Design Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
1994	J	`jnl`	On the intrinsic Rent parameter and spectra-based partitioning methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran
1994	—	`conf`	Optimal equivalent circuits for interconnect delay calculations using moments. EURO-DAC Sudhakar Muddu, Andrew B. Kahng
1994	—	`conf`	Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. EURO-DAC Chung-Wen Albert Tsao, Andrew B. Kahng
1994	A*	`conf`	Rectilinear Steiner Trees with Minimum Elmore Delay. DAC Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
1993	C	`conf`	A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. ISCAS Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng
1993	—	`conf`	Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD. EURO-DAC Kenneth D. Boese, Andrew B. Kahng, Chung-Wen Albert Tsao
1993	C	`conf`	Fidelity and Near-Optimality of Elmore-Based Routing Constructions. ICCD Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
1993	A*	`conf`	Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. DAC Charles J. Alpert, Andrew B. Kahng
1993	A*	`conf`	High-Performance Routing Trees With Identified Critical Sinks. DAC Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins
1993	J	`jnl`	Matching-based methods for high-performance clock routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Andrew B. Kahng, Gabriel Robins
1993	C	`conf`	Minimum Density Interconneciton Trees. ISCAS Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
1993	J	`jnl`	Optimal robust path planning in general environments. IEEE Trans. Robotics Autom. T. C. Hu, Andrew B. Kahng, Gabriel Robins
1993	C	`conf`	Simulated annealing of neural networks: The 'cooling' strategy reconsidered. ISCAS Kenneth D. Boese, Andrew B. Kahng
1992	A	`conf`	A new approach to effective circuit clustering. ICCAD Lars W. Hagen, Andrew B. Kahng
1992	J	`jnl`	A new class of iterative Steiner tree heuristics with good performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Gabriel Robins
1992	C	`conf`	An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
1992	J	`jnl`	DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
1992	A*	`conf`	Net Partitions Yield Better Module Partitions. DAC Jason Cong, Lars W. Hagen, Andrew B. Kahng
1992	J	`jnl`	New spectral methods for ratio cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lars W. Hagen, Andrew B. Kahng
1992	—	`conf`	On the intrinsic rent parameter and spectra-based partitioning methodologies. EURO-DAC Lars W. Hagen, Fadi J. Kurdahi, Champaka Ramachandran, Andrew B. Kahng
1992	J	`jnl`	On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Gabriel Robins
1992	J	`jnl`	Provably good performance-driven global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
1991	C	`conf`	An Effective Analog Approach to Steiner Routing. ICCD Andrew B. Kahng
1991	A	`conf`	Fast Spectral Methods for Ratio Cut Partitioning and Clustering. ICCAD Lars W. Hagen, Andrew B. Kahng
1991	A*	`conf`	High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC Andrew B. Kahng, Jason Cong, Gabriel Robins
1991	J	`jnl`	Optimal algorithms for extracting spatial regularity in images. Pattern Recognit. Lett. Andrew B. Kahng, Gabriel Robins
1991	C	`conf`	Performance-Driven Global Routing for Cell Based ICs. ICCD Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong
1990	A	`conf`	A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. ICCAD Andrew B. Kahng, Gabriel Robins
1990	—	`conf`	Every Tree is Graceful (But Some are More Graceful than Others). Applied Geometry And Discrete Mathematics T. C. Hu, Andrew B. Kahng
1989	A*	`conf`	Fast Hypergraph Partition. DAC Andrew B. Kahng