Andrej Trost

21 papers A 1B 4C 3Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
Genetically optimized massively parallel binary neural networks for intrusion detection systems.
Comput. Commun.
Tadej Murovic, Andrej Trost
2021 C conf
Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge.
DSD
Tadej Murovic, Andrej Trost
2020 C conf
Message from the Program Chairs.
DSD
Andrej Zemva, Andrej Trost
2020 J jnl
Resource-optimized combinational binary neural network circuits.
Microelectron. J.
Tadej Murovic, Andrej Trost
2019 — conf
Online VHDL Generator and Analysis Tool.
MECO
Andrej Trost, Andrej Zemva
2017 — conf
Pipeline circuit synthesis from Python code.
MECO
Andrej Trost, Andrej Zemva
2015 — conf
Configurable hardware components generator in Python.
MECO
Andrej Trost, Andrej Zemva
2014 — conf
Remote laboratory for testing processor cores in FPGA device.
MIPRO
Kristjan Saksida, Andrej Trost
2014 J jnl
Resolving Collision in EPCglobal Class-1 Gen-2 System by Utilizing the Preamble.
IEEE Trans. Wirel. Commun.
Iztok Bratuz, Andrej Vodopivec, Andrej Trost
2012 — conf
Verification structures for design of video processing circuits.
MIPRO
Andrej Trost, Andrej Zemva
2011 J jnl
A modelling-based methodology for evaluating the performance of a real-time embedded control system.
Simul. Model. Pract. Theory
Klemen Perko, Rémy Kocik, Rédha Hamouche, Andrej Trost
2011 C conf
LGMD-based bio-inspired algorithm for detecting risk of collision of a road vehicle.
ISPA
Andrej Krejan, Andrej Trost
2011 — conf
Logic emulators in digital systems education.
EUROCON
Andrej Trost, Baldomir Zajc
2009 — conf
From high-level real-time software design to low level hardware simulation: a methodology to evaluate performances of control embedded systems.
PDeS
Klemen Perko, Rémy Kocik, Rédha Hamouche, Andrej Trost
2008 J jnl
A Methodology for Supporting System-Level Design Space Exploration at Higher Levels of Abstraction.
J. Circuits Syst. Comput.
Joze Dedic, Matjaz Finc, Andrej Trost
2003 A conf
HW/SW Codesign of the MPEG-2 Video Decoder.
IPDPS
Matjaz Verderber, Andrej Zemva, Andrej Trost
2000 B conf
Educational Programmable Hardware Prototyping and Verification System.
FPL
Andrej Trost, Andrej Zemva, Baldomir Zajc
2000 B conf
Reusable DSP Functions in FPGAs.
FPL
Jernej Andrejas, Andrej Trost
1999 — conf
HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation.
EUROMICRO
Gregor Polansek, Andrej Zemva, Andrej Trost
1998 B conf
Programmabel Prototyping System for Image Processing.
FPL
Andrej Trost, Andrej Zemva, Baldomir Zajc
1996 B conf
An Experimental Programmable Environment for Prototyping Digital Circuits.
FPL
Andrej Trost, Roman Kuznar, Andrej Zemva, Baldomir Zajc