Andreas Wieferink

13 papers A 2C 1Misc 2Journal 4Unranked 3
YearRankTypeTitle / Venue / Authors
2008 — —
Retargetable processor system integration into multi-processor system on chip platforms.
Andreas Wieferink
2008 J jnl
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
Int. J. Embed. Syst.
Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr
2008 J jnl
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
Int. J. Embed. Syst.
Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr
2007 J jnl
ASIP architecture exploration for efficient IPSec encryption: A case study.
ACM Trans. Embed. Comput. Syst.
Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2005 Misc conf
Retargetable generation of TLM bus interfaces for MP-SoC platforms.
CODES+ISSS
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
2004 A conf
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
DATE
Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
2004 C conf
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.
SCOPES
Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2004 — conf
Early ISS Integration into Network-on-Chip Designs.
SAMOS
Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2004 — conf
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
SAMOS
Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2003 Misc conf
A modular simulation framework for architectural exploration of on-chip interconnection networks.
CODES+ISSS
Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
2003 — conf
Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization.
ASAP
Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann
2003 A conf
Processor/Memory Co-Exploration on Multiple Abstraction Levels.
DATE
Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
2001 J jnl
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr