Andreas Steininger

152 papers A* 1A 9B 4C 47Journal 42Unranked 49

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Circuits for Autonomous Clock Frequency Supervision. J. Circuits Syst. Comput. Clemens Scharwitzl, Andreas Steininger
2025	—	`conf`	Investigating the Effects of Permanent Faults in QDI Circuits: A Formal Perspective. ASYNC Raghda El Shehaby, Matthias Függer, Florian Huemer, Andreas Steininger
2025	—	`conf`	Muller C-Element for NEMS. ASYNC Philipp Lehninger, Axel Jantsch, Andreas Steininger, Elliott Worsey, Victor Marot, Dinesh Pamunuwa
2025	—	`conf`	SeAL: A Provably Complete Fault-Injection Tool for Asynchronous Circuits. ICECS Raghda El Shehaby, Matthias Függer, Florian Huemer, Andreas Steininger
2024	C	`conf`	An Autonomous Clock Frequency Supervision Circuit. DDECS Clemens Scharwitzl, Andreas Steininger
2024	C	`conf`	EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis. IOLTS Alessio Colucci, Andreas Steininger, Muhammad Shafique
2024	C	`conf`	SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks. IOLTS Alessio Colucci, Andreas Steininger, Muhammad Shafique
2023	J	`jnl`	ISimDL: Importance Sampling-Driven Acceleration of Fault Injection Simulations for Evaluating the Robustness of Deep Learning. CoRR Alessio Colucci, Andreas Steininger, Muhammad Shafique
2023	—	`conf`	On the Susceptibility of QDI Circuits to Transient Faults. FORMATS Raghda El Shehaby, Matthias Függer, Andreas Steininger
2023	J	`jnl`	On the Susceptibility of QDI Circuits to Transient Faults. CoRR Raghda El Shehaby, Matthias Függer, Andreas Steininger
2023	B	`conf`	SET Effects on Quasi Delay Insensitive and Synchronous Circuits. ETS Zaheer Tabassam, Andreas Steininger
2023	J	`jnl`	SHIELD: An Adaptive and Lightweight Defense against the Remote Power Side-Channel Attacks on Multi-tenant FPGAs. CoRR Mahya Morid Ahmadi, Faiq Khalid, Radha Vaidya, Florian Kriebel, Andreas Steininger, Muhammad Shafique
2023	J	`jnl`	The Hidden Behavior of a D-Latch. IEEE Trans. Circuits Syst. I Regul. Pap. Jürgen Maier, Andreas Steininger, Robert Najvirt
2023	C	`conf`	Towards Resilient Quasi Delay Insensitive Conditional Control Elements. DSD Zaheer Tabassam, Andreas Steininger
2023	—	`conf`	ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer
2022	J	`jnl`	ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. CoRR Bharath Srinivas Prabakaran, Felix Fasching, Juri Schreib, Andreas Steininger, Muhammad Shafique
2022	C	`conf`	AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. DDECS Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger
2022	C	`conf`	On SAT-Based Model Checking of Speed-Independent Circuits. DDECS Florian Huemer, Robert Najvirt, Andreas Steininger
2022	—	`conf`	SET Hardened Derivatives of QDI Buffer Template. DFT Zaheer Tabassam, Andreas Steininger
2022	J	`jnl`	Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. Jürgen Maier, Christian Hartl-Nesic, Andreas Steininger
2022	—	`conf`	Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults. DFT Raghda El Shehaby, Andreas Steininger
2022	C	`conf`	Towards Resilient QDI Pipeline Implementations. DSD Zaheer Tabassam, Andreas Steininger
2022	A	`conf`	enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. IROS Alessio Colucci, Andreas Steininger, Muhammad Shafique
2022	J	`jnl`	enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. CoRR Alessio Colucci, Andreas Steininger, Muhammad Shafique
2021	C	`ed.`	24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021 DDECS Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek
2021	C	`conf`	An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger
2021	C	`conf`	Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. DDECS Raghda El Shehaby, Andreas Steininger
2021	—	`conf`	Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam
2020	J	`jnl`	Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? CoRR Andreas Steininger, Robert Najvirt, Jürgen Maier
2020	J	`jnl`	Efficient Metastability Characterization for Schmitt-Triggers. CoRR Jürgen Maier, Andreas Steininger
2020	C	`conf`	Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. DDECS Wolfgang Duer, Andreas Steininger
2020	C	`conf`	On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. ICCD Raghda El Shehaby, Andreas Steininger
2020	J	`jnl`	Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. CoRR Jürgen Maier, Andreas Steininger
2020	J	`jnl`	The Metastable Behavior of a Schmitt-Trigger. CoRR Andreas Steininger, Jürgen Maier, Robert Najvirt
2020	—	`conf`	Timing Domain Crossing using Muller Pipelines. ASYNC Florian Huemer, Andreas Steininger
2019	J	`jnl`	An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. Thomas Polzer, Florian Huemer, Andreas Steininger
2019	—	`conf`	Efficient Metastability Characterization for Schmitt-Triggers. ASYNC Jürgen Maier, Andreas Steininger
2019	A	`conf`	International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
2019	—	`conf`	Sustainable Security & Safety: Challenges and Opportunities. CERTS Andrew Paverd, Marcus Völp, Ferdinand Brasser, Matthias Schunter, N. Asokan, Ahmad-Reza Sadeghi, Paulo Jorge Esteves Veríssimo, Andreas Steininger, Thorsten Holz
2018	—	`conf`	Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. ASYNC Florian Huemer, Andreas Steininger
2018	J	`jnl`	Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. Thomas Polzer, Florian Huemer, Andreas Steininger
2018	—	`conf`	State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner
2018	C	`conf`	Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS Florian Huemer, Thomas Polzer, Andreas Steininger
2017	—	`conf`	A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. ATS Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger
2017	J	`jnl`	A Model for the Metastability Delay of Sequential Elements. J. Circuits Syst. Comput. Thomas Polzer, Andreas Steininger
2017	J	`jnl`	A versatile architecture for long-term monitoring of single-event transient durations. Microprocess. Microsystems Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
2017	J	`jnl`	Foreword. J. Circuits Syst. Comput. Andreas Steininger, Adam Pawlak, Viera Stopjaková
2017	—	`conf`	Measuring Metastability with Free-Running Clocks. ASYNC Robert Najvirt, Thomas Polzer, Andreas Steininger
2017	C	`conf`	Measuring metastability using a time-to-digital converter. DDECS Thomas Polzer, Florian Huemer, Andreas Steininger
2017	C	`conf`	Setup for an Experimental Study of Radiation Effects in 65nm CMOS. DSD Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli
2016	C	`conf`	A general approach for comparing metastable behavior of digital CMOS gates. DDECS Thomas Polzer, Andreas Steininger
2016	C	`conf`	A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD Florian Huemer, Jakob Lechner, Andreas Steininger
2016	C	`conf`	Design and Physical Implementation of a Target ASIC for SET Experiments. DSD Varadan Savulimedu Veeravalli, Andreas Steininger
2016	C	`conf`	Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? DSD Andreas Steininger, Robert Najvirt, Jürgen Maier
2016	J	`jnl`	On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger
2016	B	`conf`	Study of a delayed single-event effect in the Muller C-element. ETS Varadan Savulimedu Veeravalli, Andreas Steininger
2016	—	`conf`	The Metastable Behavior of a Schmitt-Trigger. ASYNC Andreas Steininger, Jürgen Maier, Robert Najvirt
2015	J	`jnl`	A composable real-time architecture for replicated railway applications. J. Syst. Archit. Stefan Resch, Andreas Steininger, Christoph Scherrer
2015	—	`conf`	A pausible clock with crystal oscillator accuracy. ECCTD Robert Najvirt, Andreas Steininger
2015	—	`conf`	A versatile and reliable glitch filter for clocks. PATMOS Robert Najvirt, Andreas Steininger
2015	J	`jnl`	Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Informationstechnik Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, Varadan Savulimedu Veeravalli
2015	C	`conf`	Containment of Metastable Voltages in FPGAs. DDECS Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger
2015	J	`jnl`	Digitale Mikroelektronik in Österreich. Elektrotech. Informationstechnik Peter Rössler, Andreas Steininger
2015	C	`conf`	Enhanced Metastability Characterization Based on AC Analysis. DSD Thomas Polzer, Andreas Steininger
2015	J	`jnl`	Fault-tolerant Distributed Systems in Hardware. Bull. EATCS Danny Dolev, Matthias Függer, Christoph Lenzen, Ulrich Schmid, Andreas Steininger
2015	—	`conf`	How to Synchronize a Pausible Clock to a Reference. ASYNC Robert Najvirt, Andreas Steininger
2015	C	`conf`	Measuring the Distribution of Metastable Upsets over Time. DSD Thomas Polzer, Andreas Steininger
2015	C	`conf`	Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD Jakob Lechner, Andreas Steininger, Florian Huemer
2015	C	`conf`	Reliable and Continuous Measurement of SET Pulse Widths. DSD Varadan Savulimedu Veeravalli, Andreas Steininger
2014	A	`conf`	A tree arbiter cell for high speed resource sharing in asynchronous environments. DATE Syed Rameez Naqvi, Andreas Steininger
2014	—	`conf`	Architecture for monitoring SET propagation in 16-bit Sklansky adder. ISQED Varadan Savulimedu Veeravalli, Andreas Steininger
2014	—	`conf`	Equivalence of clock gating and synchronization with applicability to GALS communication. PATMOS Robert Najvirt, Andreas Steininger
2014	C	`conf`	Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
2014	—	`conf`	Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
2014	C	`conf`	Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. DDECS Jürgen Maier, Andreas Steininger
2014	—	`conf`	Protection of Muller-Pipelines from transient faults. ISQED Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger
2014	J	`jnl`	Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. J. Comput. Syst. Sci. Danny Dolev, Matthias Függer, Markus Posch, Ulrich Schmid, Andreas Steininger, Christoph Lenzen
2014	J	`jnl`	Runtime verification of microcontroller binary code. Sci. Comput. Program. Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
2013	C	`conf`	A Multi-Credit Flow Control scheme for asynchronous NoCs. DDECS Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger
2013	—	`conf`	An Approach for Efficient Metastability Characterization of FPGAs through the Designer. ASYNC Thomas Polzer, Andreas Steininger
2013	—	`conf`	An SET Tolerant Tree Arbiter Cell. ASYNC Syed Rameez Naqvi, Andreas Steininger, Jakob Lechner
2013	J	`jnl`	An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek
2013	—	`conf`	Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. ASYNC Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger
2013	C	`conf`	Digital Late-Transition Metastability Simulation Model. DSD Thomas Polzer, Andreas Steininger
2013	—	`conf`	Metastability characterization for muller C-elements. PATMOS Thomas Polzer, Andreas Steininger
2013	—	`conf`	SET propagation in micropipelines. PATMOS Thomas Polzer, Andreas Steininger
2013	—	`conf`	Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. SASSUR@SAFECOMP Stefan Resch, Andreas Steininger, Christoph Scherrer
2012	C	`conf`	Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
2012	A	`conf`	Designing FlexRay-based automotive architectures: A holistic OEM approach. DATE Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich
2012	J	`jnl`	FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs CoRR Danny Dolev, Matthias Függer, Christoph Lenzen, Markus Posch, Ulrich Schmid, Andreas Steininger
2012	—	`conf`	Muller C-Element Metastability Containment. PATMOS Thomas Polzer, Andreas Steininger, Jakob Lechner
2012	C	`conf`	Protecting an Asynchronous NoC against Transient Channel Faults. DSD Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger
2012	C	`conf`	Radiation-tolerant combinational gates - an implementation based comparison. DDECS Varadan Savulimedu Veeravalli, Andreas Steininger
2011	C	`ed.`	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011 DDECS Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus
2011	B	`conf`	Automated Test-Trace Inspection for Microcontroller Binary Code. RV Thomas Reinbacher, Jörg Brauer, Daniel Schachinger, Andreas Steininger, Stefan Kowalewski
2011	C	`conf`	Past Time LTL Runtime Verification for Microcontroller Binary Code. FMICS Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
2011	J	`jnl`	Replicated processors on a single die - How independently do they fail? Elektrotech. Informationstechnik Peter Tummeltshammer, Andreas Steininger
2011	J	`jnl`	VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. J. Electr. Comput. Eng. Gottfried Fuchs, Andreas Steininger
2010	C	`ed.`	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010 DDECS Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann
2010	C	`conf`	A deterministic approach for hardware fault injection in asynchronous QDI logic. DDECS Werner Friesenbichler, Thomas Panhofer, Andreas Steininger
2010	C	`conf`	Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS Marcus Jeitler, Jakob Lechner, Andreas Steininger
2010	—	`conf`	Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. DSN Workshops Thomas Panhofer, Werner Friesenbichler, Andreas Steininger
2010	—	`conf`	Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. AHS Thomas Panhofer, Werner Friesenbichler, Andreas Steininger
2010	—	`conf`	Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. MEMICS Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
2009	C	`conf`	A Metastability-Free Multi-synchronous Communication Scheme for SoCs. SSS Thomas Polzer, Thomas Handl, Andreas Steininger
2009	J	`jnl`	Is Asynchronous Logic More Robust Than Synchronous Logic?. IEEE Trans. Dependable Secur. Comput. Babak Rahbaran, Andreas Steininger
2009	C	`conf`	On the Risk of Fault Coupling over the Chip Substrate. DSD Peter Tummeltshammer, Andreas Steininger
2009	—	`conf`	On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. ASYNC Gottfried Fuchs, Matthias Függer, Andreas Steininger
2009	C	`conf`	On the role of the power supply as an entry for common cause faults - An experimental analysis. DDECS Peter Tummeltshammer, Andreas Steininger
2009	A	`conf`	Power supply induced common cause faults-experimental assessment of potential countermeasures. DSN Peter Tummeltshammer, Andreas Steininger
2009	A	`conf`	Remote measurement of local oscillator drifts in FlexRay networks. DATE Eric Armengaud, Andreas Steininger
2009	J	`jnl`	Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach. IEEE Trans. Ind. Informatics Matthias Függer, Eric Armengaud, Andreas Steininger
2009	C	`conf`	Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. DSD Werner Friesenbichler, Andreas Steininger
2008	—	`conf`	An investigation of the clique problem in FlexRay. SIES Paul Milbredt, Martin Horauer, Andreas Steininger
2008	—	`conf`	Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. DELTA Paul Milbredt, Andreas Steininger, Martin Horauer
2008	A	`conf`	Automated generation of explicit connectors for component based hardware/software interaction in embedded real-time systems. IPDPS Wolfgang Forster, Christof Kutschera, Andreas Steininger, Karl M. Göschka
2008	—	`conf`	Error Containment in the Presence of Metastability. Fault-Tolerant Distributed Algorithms on VLSI Chips Andreas Steininger
2008	—	`conf`	Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. CVPR Workshops Kristian Ambrosch, Martin Humenberger, Wilfried Kubinger, Andreas Steininger
2008	J	`jnl`	Flexible Hardware-Based Stereo Matching. EURASIP J. Embed. Syst. Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, Andreas Steininger
2008	C	`conf`	Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. DSD Gottfried Fuchs, Matthias Függer, Ulrich Schmid, Andreas Steininger
2008	J	`jnl`	Towards a Systematic Test for Embedded Automotive Communication Systems. IEEE Trans. Ind. Informatics Eric Armengaud, Andreas Steininger, Martin Horauer
2007	C	`conf`	A Fail-Silent Reconfigurable Superscalar Processor. PRDC Thomas Kottke, Andreas Steininger
2007	J	`jnl`	FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung. Elektrotech. Informationstechnik Ulrich Schmid, Andreas Steininger, Manfred Sust
2007	A*	`conf`	Hardware implementation of an SAD based stereo vision algorithm. CVPR Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, Andreas Steininger
2007	C	`conf`	The effect of quartz drift on convergence-average based clock synchronization. ETFA Eric Armengaud, Andreas Steininger, Alexander Hanzlik
2006	A	`conf`	A Reconfigurable Generic Dual-Core Architecture. DSN Thomas Kottke, Andreas Steininger
2006	C	`conf`	Automatic Parameter Identi cation in FlexRay based Automotive Communication Networks. ETFA Eric Armengaud, Andreas Steininger, Martin Horauer
2006	—	`conf`	Recovery Mechanisms for Dual Core Architectures. DFT Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter
2006	C	`conf`	Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods. DSD Martin Delvai, Andreas Steininger
2006	—	`conf`	VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. DFT Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf
2005	A	`conf`	A structured approach for the systematic test of embedded automotive communication systems. ITC Eric Armengaud, Florian Rothensteiner, Andreas Steininger, Roman Pallierer, Martin Horauer, Martin Zauner
2005	C	`conf`	Efficient stimulus generation for testing embedded distributed systems the FlexRay example. ETFA Eric Armengaud, Andreas Steininger, Martin Horauer
2004	J	`jnl`	A Generic Dual Core Architecture with Error Containment. Comput. Artif. Intell. Thomas Kottke, Andreas Steininger
2004	—	`conf`	Built-in Fault Injection in Hardware - The FIDYCO Example. DELTA Babak Rahbaran, Andreas Steininger, Thomas Handl
2004	—	`conf`	Embedded Real-Time-Tracer - An Approach with IDE. WISES Babak Rahbaran, Matthias Függer, Andreas Steininger
2003	J	`jnl`	A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. IEEE Trans. Reliab. Karl Thaller, Andreas Steininger
2003	—	`conf`	Built-In Fault Injectors - The Logical Continuation of BIST? WISES Andreas Steininger, Babak Rahbaran, Thomas Handl
2003	J	`jnl`	Dealing with dormant faults in an embedded fault-tolerant computer system. IEEE Trans. Reliab. Christoph Scherrer, Andreas Steininger
2003	B	`conf`	Processor Support for Temporal Predictability - The SPEAR Design Example. ECRTS Martin Delvai, Wolfgang Huber, Peter P. Puschner, Andreas Steininger
2002	J	`jnl`	Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault Injection Experiments. IEEE Trans. Computers Andreas Steininger, Christoph Scherrer
2002	C	`conf`	Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example. ICCD Andreas Steininger, Johann Vilanek
2001	—	`conf`	How to Tune the MTTF of a Fail-Silent System. DFT Andreas Steininger, Christoph Scherrer
2000	—	`conf`	How Does Resource Utilization Affect Fault Tolerance? DFT Andreas Steininger, Christoph Scherrer
2000	J	`jnl`	Testing and built-in self-test - A survey. J. Syst. Archit. Andreas Steininger
1999	J	`jnl`	Economic Online Self-Test in the Time-Triggered Architecture. IEEE Des. Test Comput. Andreas Steininger, Christopher Temple
1999	—	`conf`	On the Necessity of On-Line-BIST in Safety-Critical Applications - A Case Study. FTCS Andreas Steininger, Christoph Scherrer
1999	J	`jnl`	On the determination of dynamic errors for rise time measurement with an oscilloscope. IEEE Trans. Instrum. Meas. Christoph Mittermayer, Andreas Steininger
1997	—	`conf`	On Finding an Optimal Combination of Error Detection Mechanisms Based on Results of Fault Injection Experiments. FTCS Andreas Steininger, Christoph Scherrer
1995	—	`conf`	A Model for the Analysis of the Fault Injection Process. FTCS Andreas Steininger, Herbert Schweinzer
1993	J	`jnl`	The design of a fail-silent processing node for the predictable hard real-time system MARS. Distributed Syst. Eng. Johannes Reisinger, Andreas Steininger
1991	—	`conf`	Can the advantages of RISC be utilized in real time systems? RTS Andreas Steininger, Herbert Schweinzer
1991	J	`jnl`	Towards an optimal combination of error detection mechanisms. Microprocessing and Microprogramming Andreas Steininger, Herbert Schweinzer