Andreas Lööw

16 papers A* 1A 3B 3C 1Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
2025 J jnl
Compositional Symbolic Execution for the Next 700 Memory Models (Extended Version).
CoRR
Andreas Lööw, Seung Hoon Park, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Opale Sjöstedt, Philippa Gardner
2025 J jnl
Compositional Symbolic Execution for the Next 700 Memory Models.
Proc. ACM Program. Lang.
Andreas Lööw, Seung Hoon Park, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Opale Sjöstedt, Philippa Gardner
2025 J jnl
The Simulation Semantics of Synthesisable Verilog.
CoRR
Andreas Lööw
2025 J jnl
The Simulation Semantics of Synthesisable Verilog.
Proc. ACM Program. Lang.
Andreas Lööw
2024 J jnl
Compositional Symbolic Execution for Correctness and Incorrectness Reasoning (Artifact).
Dagstuhl Artifacts Ser.
Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Nat Karmios, Petar Maksimovic, Philippa Gardner
2024 J jnl
Compositional Symbolic Execution for Correctness and Incorrectness Reasoning (Extended Version).
CoRR
Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Petar Maksimovic, Philippa Gardner
2024 A conf
Compositional Symbolic Execution for Correctness and Incorrectness Reasoning.
ECOOP
Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Petar Maksimovic, Philippa Gardner
2024 A conf
Matching Plans for Frame Inference in Compositional Reasoning.
ECOOP
Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Petar Maksimovic, Philippa Gardner
2023 A conf
Exact Separation Logic: Towards Bridging the Gap Between Verification and Bug-Finding.
ECOOP
Petar Maksimovic, Caroline Cronjäger, Andreas Lööw, Julian Sutherland, Philippa Gardner
2023 B conf
Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor.
FMCAD
Ning Dong, Roberto Guanciale, Mads Dam, Andreas Lööw
2022 C conf
A small, but important, concurrency problem in Verilog's semantics? (Work in progress).
MEMOCODE
Andreas Lööw
2022 J jnl
Exact Separation Logic.
CoRR
Petar Maksimovic, Caroline Cronjäger, Julian Sutherland, Andreas Lööw, Sacha-Élie Ayoun, Philippa Gardner
2022 B conf
Reconciling Verified-Circuit Development and Verilog Development.
FMCAD
Andreas Lööw
2021 B conf
Lutsig: a verified Verilog compiler for verified circuit development.
CPP
Andreas Lööw
2019 — conf
A proof-producing translator for verilog development in HOL.
FormaliSE@ICSE
Andreas Lööw, Magnus O. Myreen
2019 A* conf
Verified compilation on a verified processor.
PLDI
Andreas Lööw, Ramana Kumar, Yong Kiam Tan, Magnus O. Myreen, Michael Norrish, Oskar Abrahamsson, Anthony C. J. Fox