Andreas Hansson

36 papers A* 1A 4B 4C 2Misc 3Journal 12Unranked 9

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	The gem5 Simulator: Version 20.0+. CoRR Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian
2018	J	`jnl`	Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact. CoRR Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn
2017	J	`jnl`	Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Anup Das, Sheng Yang, Bashir M. Al-Hashimi, Geoff V. Merrett
2017	J	`jnl`	DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. Int. J. Parallel Program. Christian Weis, Abdul Mutaal, Omar Naji, Matthias Jung, Andreas Hansson, Norbert Wehn
2017	—	`conf`	Integrating DRAM power-down modes in gem5 and quantifying their impact. MEMSYS Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn
2016	B	`conf`	Elastic traces for fast and accurate system performance exploration. ISPASS Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson
2016	—	`conf`	Exploring system performance using elastic traces: Fast, accurate and portable. SAMOS Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung, Norbert Wehn
2016	—	`conf`	Thermally-aware composite run-time CPU power models. PATMOS Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Domenico Balsamo, Geoff V. Merrett, Bashir M. Al-Hashimi
2015	B	`conf`	A full-system approach to analyze the impact of next-generation mobile flash storage. ISPASS René de Jong, Andreas Hansson
2015	—	`conf`	A high-level DRAM timing, power and area exploration tool. SAMOS Omar Naji, Christian Weis, Matthias Jung, Norbert Wehn, Andreas Hansson
2015	A	`conf`	Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones. ISLPED Anup Das, Matthew J. Walker, Andreas Hansson, Bashir M. Al-Hashimi, Geoff V. Merrett
2015	—	`conf`	Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. ISVLSI Christian Weis, Matthias Jung, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson
2014	B	`conf`	Simulating DRAM controllers for future system architecture exploration. ISPASS Andreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas F. Wenisch, Aniruddha N. Udipi
2013	—	`conf`	Applying of Quality of Experience to system optimisation. PATMOS Sascha Bischoff, Andreas Hansson, Bashir M. Al-Hashimi
2013	B	`conf`	Introducing DVFS-Management in a Full-System Simulator. MASCOTS Vasileios Spiliopoulos, Akash Bagdia, Andreas Hansson, Peter Aldworth, Stefanos Kaxiras
2011	J	`jnl`	A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications. Des. Autom. Embed. Syst. Andreas Hansson, Kees Goossens
2011	—	`ch.`	Composability and Predictability for Independent Application Development, Verification, and Execution. Multiprocessor System-on-Chip Benny Akesson, Anca Mariana Molnos, Andreas Hansson, Jude Angelo Ambrose, Kees Goossens
2011	J	`jnl`	Design and implementation of an operating system for composable processor sharing. Microprocess. Microsystems Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens
2010	—	`conf`	Conservative application-level performance analysis through simulation of MPSoCs. ESTIMedia Andrew Nelson, Andreas Hansson, Henk Corporaal, Kees Goossens
2010	A*	`conf`	The aethereal network on chip after ten years: goals, evolution, lessons, and future. DAC Kees Goossens, Andreas Hansson
2009	A	`conf`	Aelite: A flit-synchronous Network on Chip with composable and predictable services. DATE Andreas Hansson, Mahesh Subburaman, Kees Goossens
2009	Misc	`conf`	An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. CODES+ISSS Andreas Hansson, Kees Goossens
2009	J	`jnl`	CoMPSoC: A template for composable and predictable multi-processor system on chips. ACM Trans. Design Autom. Electr. Syst. Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken
2009	C	`conf`	Composable Resource Sharing Based on Latency-Rate Servers. DSD Benny Akesson, Andreas Hansson, Kees Goossens
2009	J	`jnl`	Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Comput. Digit. Tech. Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij
2009	J	`jnl`	Multi-processor programming in the embedded system curriculum. SIGBED Rev. Andreas Hansson, Benny Akesson, Jef L. van Meerbergen
2008	J	`jnl`	A monitoring-aware network-on-chip design flow. J. Syst. Archit. Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten
2008	—	`conf`	Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. NOCS Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij
2007	J	`jnl`	A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic. VLSI Design Andreas Hansson, Kees Goossens, Andrei Radulescu
2007	J	`jnl`	Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip. VLSI Design Andreas Hansson, Kees Goossens, Andrei Radulescu
2007	Misc	`conf`	Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. CODES+ISSS Andreas Hansson, Martijn Coenen, Kees Goossens
2007	A	`conf`	Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. DATE Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal
2007	—	`conf`	Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. NOCS Andreas Hansson, Kees Goossens
2007	A	`conf`	Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. DATE Andreas Hansson, Martijn Coenen, Kees Goossens
2006	C	`conf`	A Monitoring-Aware Network-on-Chip Design Flow. DSD Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten
2005	Misc	`conf`	A unified approach to constrained mapping and routing on network-on-chip architectures. CODES+ISSS Andreas Hansson, Kees Goossens, Andrei Radulescu