Andreas G. Veneris

169 papers A* 6A 31B 6C 13Misc 3Journal 49Unranked 60

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	An Assessment Framework to Offline Functionality in Central Bank Digital Currencies. BRAINS Vladyslav Nekriach, Panagiotis Michalopoulos, Cyrus Minwalla, Andreas G. Veneris
2025	J	`jnl`	Balancing Compliance and Privacy in Offline CBDC Transactions Using a Secure Element-based System. CoRR Panagiotis Michalopoulos, Anthony Mack, Cameron Clark, Linus Chen, Johannes Sedlmeir, Andreas G. Veneris
2025	J	`jnl`	HEMVM: A Heterogeneous Blockchain Framework for Interoperable Virtual Machines. Proc. ACM Program. Lang. Vladyslav Nekriach, Sidi Mohamed Beillahi, Chenxing Li, Peilun Li, Ming Wu, Andreas G. Veneris, Fan Long
2025	B	`conf`	Modeling Loss-Versus-Rebalancing in Automated Market Makers via Continuous-Installment Options. AFT Srisht Fateh Singh, Reina Ke Xin Li, Samuel Gaskin, Yuntao Wu, Jeffrey Klinck, Panagiotis Michalopoulos, Zissis Poulos, Andreas G. Veneris
2025	J	`jnl`	Option Contracts in the DeFi Ecosystem: Opportunities, Solutions, and Technical Challenges. Int. J. Netw. Manag. Srisht Fateh Singh, Vladyslav Nekriach, Panagiotis Michalopoulos, Andreas G. Veneris, Jeffrey Klinck
2025	J	`jnl`	Privacy and Compliance Design Options in Offline Central Bank Digital Currencies. IEEE Trans. Netw. Serv. Manag. Panagiotis Michalopoulos, Odunayo Olowookere, Nadia Pocher, Johannes Sedlmeir, Andreas G. Veneris, Poonam Puri
2025	J	`jnl`	Secure Smart Contract with Control Flow Integrity. CoRR Zhiyang Chen, Sidi Mohamed Beillahi, Pasha Barahimi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long
2025	J	`jnl`	VerifyThisBench: Generating Code, Specifications, and Proofs All at Once. CoRR Xun Deng, Sicheng Zhong, Andreas G. Veneris, Fan Long, Xujie Si
2024	J	`jnl`	BAKUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance. CoRR Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
2024	C	`conf`	BakUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance. ICBC Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
2024	C	`conf`	Compliance Design Options for Offline CBDCs: Balancing Privacy and AML/CFT. ICBC Panagiotis Michalopoulos, Odunayo Olowookere, Nadia Pocher, Johannes Sedlmeir, Andreas G. Veneris, Poonam Puri
2024	J	`jnl`	Deeper: A shared liquidity decentralized exchange design for low trading volume tokens to enhance average liquidity. Int. J. Netw. Manag. Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
2024	J	`jnl`	Innovations in Blockchain for Crypto Assets and Exchanges. Int. J. Netw. Manag. James Won-Ki Hong, Andreas G. Veneris, Hongtaek Ju, Taeyeol Jeong, Changhoon Kang
2024	J	`jnl`	LMPT: A Novel Authenticated Data Structure to Eliminate Storage Bottlenecks for High Performance Blockchains. IEEE Trans. Netw. Serv. Manag. Jemin Andrew Choi, Sidi Mohamed Beillahi, Srisht Fateh Singh, Panagiotis Michalopoulos, Peilun Li, Andreas G. Veneris, Fan Long
2024	—	`conf`	On Tokenizing Securities in Contemporary Decentralized Finance Ecosystems. BRAINS Reina Ke Xin Li, Srisht Fateh Singh, Andreas G. Park, Andreas G. Veneris
2024	C	`conf`	Option Contracts in the DeFi Ecosystem: Motivation, Solutions, & Technical Challenges. ICBC Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
2024	A*	`conf`	Safeguarding DeFi Smart Contracts against Oracle Deviations. ICSE Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long
2024	J	`jnl`	Safeguarding DeFi Smart Contracts against Oracle Deviations. CoRR Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long
2023	—	`conf`	A Robust Front-Running Methodology for Malicious Flash- Loan DeFi Attacks. DAPPS Xun Deng, Zihan Zhao, Sidi Mohamed Beillahi, Han Du, Cyrus Minwalla, Keerthi Nelaturu, Andreas G. Veneris, Fan Long
2023	J	`jnl`	Correct-by-Design Interacting Smart Contracts and a Systematic Approach for Verifying ERC20 and ERC721 Contracts With VeriSolid. IEEE Trans. Dependable Secur. Comput. Keerthi Nelaturu, Anastasia Mavridou, Emmanouela Stachtiari, Andreas G. Veneris, Aron Laszka
2023	C	`conf`	DEEPER: Enhancing Liquidity in Concentrated Liquidity AMM DEX via Sharing. ICBC Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
2023	—	`conf`	Gas Optimization Patterns in Move Smart Contracts on the Aptos Blockchain. BRAINS Eric Keilty, Keerthi Nelaturu, Anastasia Kastania, Andreas G. Veneris
2023	—	`conf`	Inducing Trust in Blockchain-enabled IoT Marketplaces Through Reputation and Dispute Resolution. MetaCom Panagiotis Michalopoulos, Srisht Fateh Singh, Andreas G. Veneris
2023	C	`conf`	Möbius: an Atomic State Sharding Design for Account-Based Blockchains. ICBC Srisht Fateh Singh, Panagiotis Michalopoulos, Sidi Mohamed Beillahi, Andreas G. Veneris, Fan Long
2023	—	`conf`	Natural Language-Based Model-Checking Framework for Move Smart Contracts. SDS Keerthi Nelaturu, Eric Keilty, Andreas G. Veneris
2022	C	`conf`	Automated Auditing of Price Gouging TOD Vulnerabilities in Smart Contracts. ICBC Sidi Mohamed Beillahi, Eric Keilty, Keerthi Nelaturu, Andreas G. Veneris, Fan Long
2022	J	`jnl`	Guest Editorial: Special Issue on Recent Advances on Blockchain for Network and Service Management. IEEE Trans. Netw. Serv. Manag. Salil S. Kanhere, Andreas G. Veneris, Sachiko Yoshihama, Sandip Chakraborty, Ori Rottenstreich, Marta Beltrán Pardo, Bruno Rodriguez
2022	C	`conf`	LMPTs: Eliminating Storage Bottlenecks for Processing Blockchain Transactions. ICBC Jemin Andrew Choi, Sidi Mohamed Beillahi, Peilun Li, Andreas G. Veneris, Fan Long
2022	J	`jnl`	Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. IEEE Trans. Netw. Serv. Manag. Nadia Pocher, Andreas G. Veneris
2022	J	`jnl`	SigVM: enabling event-driven execution for truly decentralized smart contracts. Proc. ACM Program. Lang. Zihan Zhao, Sidi Mohamed Beillahi, Ryan Song, Yuxi Cai, Andreas G. Veneris, Fan Long
2022	J	`jnl`	Truthful Decentralized Blockchain Oracles. Int. J. Netw. Manag. Yuxi Cai, Nafis Irtija, Eirini-Eleni Tsiropoulou, Andreas G. Veneris
2021	—	`conf`	Blockchain for V2X: A Taxonomy of Design Use Cases and System Requirements. BRAINS James Meijers, Edward Au, Yuxi Cai, Hans-Arno Jacobsen, Shashank Motepalli, Robert Sun, Andreas G. Veneris, Gengrui Zhang, Shiquan Zhang
2021	—	`conf`	Cost-Effective Blockchain-based IoT Data Marketplaces with a Credit Invariant. IEEE ICBC James Meijers, Guntur Dharma Putra, Grammateia Kotsialou, Salil S. Kanhere, Andreas G. Veneris
2021	—	`conf`	Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. IEEE ICBC Nadia Pocher, Andreas G. Veneris
2021	J	`jnl`	SigVM: Toward Fully Autonomous Smart Contracts. CoRR Ryan Song, Zihan Zhao, Yuxi Cai, Andreas G. Veneris, Fan Long
2021	—	`conf`	Smart Contracts Refinement for Gas Optimization. BRAINS Keerthi Nelaturu, Sidi Mohamed Beillahi, Fan Long, Andreas G. Veneris
2020	—	`conf`	A Truth-Inducing Sybil Resistant Decentralized Blockchain Oracle. BRAINS Yuxi Cai, Georgios Fragkos, Eirini-Eleni Tsiropoulou, Andreas G. Veneris
2020	—	`conf`	Engineering Economics in the Conflux Network. BRAINS Yuxi Cai, Fan Long, Andreas G. Park, Andreas G. Veneris
2020	J	`jnl`	On Public Crowdsource-Based Mechanisms for a Decentralized Blockchain Oracle. IEEE Trans. Engineering Management Keerthi Nelaturu, John Adler, Marco Merlini, Ryan Berryhill, Neil Veira, Zissis Poulos, Andreas G. Veneris
2020	J	`jnl`	Searching for Bugs Using Probabilistic Suspect Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Neil Veira, Zissis Poulos, Andreas G. Veneris
2020	—	`conf`	Verified Development and Deployment of Multiple Interacting Smart Contracts with VeriSolid. IEEE ICBC Keerthi Nelaturu, Anastasia Mavridou, Andreas G. Veneris, Aron Laszka
2019	B	`conf`	Chasing Minimal Inductive Validity Cores in Hardware Model Checking. FMCAD Ryan Berryhill, Andreas G. Veneris
2019	—	`conf`	On Public Decentralized Ledger Oracles via a Paired-Question Protocol. IEEE ICBC Marco Merlini, Neil Veira, Ryan Berryhill, Andreas G. Veneris
2019	J	`jnl`	Special Drawing Rights in a New Decentralized Century. CoRR Andreas G. Veneris, Andreas G. Park
2019	—	`conf`	Suspect2vec: a suspect prediction model for directed RTL debugging. ASP-DAC Neil Veira, Zissis Poulos, Andreas G. Veneris
2019	A*	`conf`	Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations. IJCAI Neil Veira, Brian Keng, Kanchana Padmanabhan, Andreas G. Veneris
2018	—	`conf`	Astraea: A Decentralized Blockchain Oracle. iThings/GreenCom/CPSCom/SmartData John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania
2018	J	`jnl`	Astraea: A Decentralized Blockchain Oracle. CoRR John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania
2018	J	`jnl`	Efficient suspect selection in unreachable state diagnosis. Ann. Math. Artif. Intell. Ryan Berryhill, Andreas G. Veneris
2018	J	`jnl`	Failure Triage in RTL Regression Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zissis Poulos, Andreas G. Veneris
2018	A	`conf`	Finding All Minimal Safe Inductive Sets. SAT Ryan Berryhill, Alexander Ivrii, Andreas G. Veneris
2018	J	`jnl`	Methodologies for Diagnosis of Unreachable States via Property Directed Reachability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ryan Berryhill, Andreas G. Veneris
2018	A	`conf`	Suspect set prediction in RTL bug hunting. DATE Neil Veira, Zissis Poulos, Andreas G. Veneris
2017	—	`conf`	An extensible perceptron framework for revision RTL debug automation. ASP-DAC John Adler, Ryan Berryhill, Andreas G. Veneris
2017	A*	`conf`	Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism. ICDM Koushik Pal, Zissis Poulos, Edward Kim, Andreas G. Veneris
2017	—	`conf`	Learning lemma support graphs in Quip and IC3. IVSW Ryan Berryhill, Neil Veira, Andreas G. Veneris, Zissis Poulos
2017	B	`conf`	Learning support sets in IC3 and Quip: The good, the bad, and the ugly. FMCAD Ryan Berryhill, Alexander Ivrii, Neil Veira, Andreas G. Veneris
2017	J	`jnl`	Leveraging Software Configuration Management in Automated RTL Design Debug. IEEE Des. Test John Adler, Andreas G. Veneris
2016	—	`conf`	A complete approach to unreachable state diagnosability via property directed reachability. ASP-DAC Ryan Berryhill, Andreas G. Veneris
2016	Misc	`conf`	Efficient Selection of Suspect Sets in Unreachable State Diagnosis. ISAIM Ryan Berryhill, Andreas G. Veneris
2016	J	`jnl`	Exemplar-based Failure Triage for Regression Design Debugging. J. Electron. Test. Zissis Poulos, Andreas G. Veneris
2016	—	`conf`	On simulation-based metrics that characterize the behavior of RTL errors. SummerSim Zissis Poulos, Ryan Berryhill, John Adler, Andreas G. Veneris
2016	—	`conf`	Revision debug with non-linear version history in regression verification. IVSW John Adler, Ryan Berryhill, Andreas G. Veneris
2016	A	`conf`	Root-cause analysis for memory-locked errors. DATE John Adler, Djordje Maksimovic, Andreas G. Veneris
2015	A	`conf`	Automated rectification methodologies to functional state-space unreachability. DATE Ryan Berryhill, Andreas G. Veneris
2015	C	`conf`	Clustering-based revision debug in regression verification. ICCD Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos
2015	—	`conf`	Constructing stability-based clock gating with hierarchical clustering. PATMOS Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris
2015	—	`conf`	Exemplar-based failure triage for regression design debugging. LATS Zissis Poulos, Andreas G. Veneris
2015	—	`conf`	FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne
2015	C	`conf`	Mining simulation metrics for failure triage in regression testing. IOLTS Zissis Poulos, Andreas G. Veneris
2014	—	`conf`	Automated debugging of missing assumptions. ASP-DAC Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le
2014	A	`conf`	Clustering-based failure triage for RTL regression debugging. ITC Zissis Poulos, Andreas G. Veneris
2014	J	`jnl`	Debugging RTL Using Structural Dominance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hratch Mangassarian, Bao Le, Andreas G. Veneris
2014	A	`conf`	Multiple clock domain synchronization in a QBF-based verification environment. ICCAD Djordje Maksimovic, Bao Le, Andreas G. Veneris
2014	—	`conf`	Simulation and satisfiability guided counter-example triage for RTL design debugging. ISQED Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le
2013	C	`conf`	A failure triage engine based on error trace signature extraction. IOLTS Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris
2013	C	`conf`	Accelerating post silicon debug of deep electrical faults. IOLTS Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos
2013	A	`conf`	Early detection of current hot spots in power gated designs. ISLPED Dipanjan Sengupta, Erhan Ergin, Andreas G. Veneris
2013	J	`jnl`	Path-Directed Abstraction and Refinement for SAT-Based Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brian Keng, Andreas G. Veneris
2013	—	`conf`	Reviving erroneous stability-based clock-gating using partial Max-SAT. ASP-DAC Bao Le, Dipanjan Sengupta, Andreas G. Veneris
2012	—	`conf`	Automated data analysis techniques for a modern silicon debug environment. ASP-DAC Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
2012	B	`conf`	Automated debugging of missing input constraints in a formal verification environment. FMCAD Brian Keng, Andreas G. Veneris
2012	J	`jnl`	Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici
2012	—	`conf`	Lazy suspect-set computation: fault diagnosis for deep electrical bugs. ACM Great Lakes Symposium on VLSI Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov
2012	A	`conf`	Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le
2012	J	`jnl`	Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm
2012	J	`jnl`	Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov
2012	A	`conf`	Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris
2012	—	`conf`	On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita
2012	A*	`conf`	Path directed abstraction and refinement in SAT-based design debugging. DAC Brian Keng, Andreas G. Veneris
2011	A	`conf`	Automated debugging of SystemVerilog assertions. DATE Brian Keng, Sean Safarpour, Andreas G. Veneris
2011	J	`jnl`	Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton
2011	A	`conf`	Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour
2011	—	`conf`	From RTL to silicon: The case for automated debug. ASP-DAC Andreas G. Veneris, Brian Keng, Sean Safarpour
2011	—	`conf`	Managing complexity in design debugging with sequential abstraction and refinement. ASP-DAC Brian Keng, Andreas G. Veneris
2011	—	`conf`	Sequence pair based voltage island floorplanning. IGCC Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh
2011	J	`jnl`	Two-Stage, Pipelined Register Renaming. IEEE Trans. Very Large Scale Integr. Syst. Elham Safi, Andreas Moshovos, Andreas G. Veneris
2010	—	`conf`	An Automated Framework for Correction and Debug of PSL Assertions. MTV Brian Keng, Andreas G. Veneris, Sean Safarpour
2010	J	`jnl`	Automated Design Debugging With Maximum Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris
2010	—	`conf`	Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
2010	J	`jnl`	Bounded Model Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brian Keng, Sean Safarpour, Andreas G. Veneris
2010	A	`conf`	Leveraging dominators for preprocessing QBF. DATE Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus
2010	—	`conf`	Managing verification error traces with bounded model debugging. ASP-DAC Sean Safarpour, Andreas G. Veneris, Farid N. Najm
2010	J	`jnl`	On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. IEEE Trans. Very Large Scale Integr. Syst. Elham Safi, Andreas Moshovos, Andreas G. Veneris
2010	J	`jnl`	Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. IEEE Trans. Computers Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti
2009	—	`conf`	A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ICSAMOS Elham Safi, Andreas Moshovos, Andreas G. Veneris
2009	J	`jnl`	Automated Design Debugging With Abstraction and Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sean Safarpour, Andreas G. Veneris
2009	A	`conf`	Automated data analysis solutions to silicon debug. DATE Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
2009	—	`conf`	Automated debugging with high level abstraction and refinement. HLDVT Sean Safarpour, Andreas G. Veneris
2009	B	`conf`	Scaling VLSI design debugging with interpolation. FMCAD Brian Keng, Andreas G. Veneris
2009	A	`conf`	Sequential logic rectifications with approximate SPFDs. DATE Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith
2009	—	`conf`	Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI Yibin Chen, Sean Safarpour, Andreas G. Veneris, João Marques-Silva
2009	A*	`conf`	The day Sherlock Holmes decided to do EDA. DAC Andreas G. Veneris, Sean Safarpour
2008	A	`conf`	A physical level study and optimization of CAM-based checkpointed register alias table. ISLPED Elham Safi, Andreas Moshovos, Andreas G. Veneris
2008	A	`conf`	A succinct memory model for automated design debugging. ICCAD Brian Keng, Hratch Mangassarian, Andreas G. Veneris
2008	J	`jnl`	Improved SAT-based Reachability Analysis with Observability Don't Cares. J. Satisf. Boolean Model. Comput. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2008	J	`jnl`	L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. IEEE Trans. Very Large Scale Integr. Syst. Elham Safi, Andreas Moshovos, Andreas G. Veneris
2008	C	`conf`	On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
2007	A	`conf`	A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith
2007	A	`conf`	Abstraction and refinement techniques in automated design debugging. DATE Sean Safarpour, Andreas G. Veneris
2007	—	`conf`	Automating Logic Rectification by Approximate SPFDs. ASP-DAC Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton
2007	B	`conf`	Improved Design Debugging Using Maximum Satisfiability. FMCAD Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah
2007	A	`conf`	Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007	A	`conf`	On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni
2007	—	`conf`	Trace Compaction using SAT-based Reachability Analysis. ASP-DAC Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian
2006	—	`conf`	Abstraction and Refinement Techniques in Automated Design Debugging. MTV Sean Safarpour, Andreas G. Veneris
2006	A*	`conf`	Efficient SAT-based Boolean matching for FPGA technology mapping. DAC Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
2006	J	`jnl`	Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. Very Large Scale Integr. Syst. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
2006	C	`conf`	Integrating observability don't cares in all-solution SAT solvers. ISCAS Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2006	A	`conf`	L-CBF: a low-power, fast counting bloom filter architecture. ISLPED Elham Safi, Andreas Moshovos, Andreas G. Veneris
2006	A	`conf`	On the relation between simulation-based and SAT-based diagnosis. DATE Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2006	A	`conf`	Seamless Integration of SER in Rewiring-Based Design Space Exploration. ITC Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
2006	Misc	`conf`	Session Abstract. VTS Andreas G. Veneris, Yiorgos Makris
2005	—	`conf`	Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
2005	A	`conf`	Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
2005	J	`jnl`	Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas
2005	J	`jnl`	Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electron. Test. Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi
2005	J	`jnl`	Incremental Design Debugging in a Logic Synthesis Environment. J. Electron. Test. Andreas G. Veneris, Jiang Brandon Liu
2005	J	`jnl`	Incremental fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Brandon Liu, Andreas G. Veneris
2005	—	`conf`	Post-Verification Debugging of Hierarchical Designs. MTV Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005	A	`conf`	Post-verification debugging of hierarchical designs. ICCAD Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005	—	`conf`	Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
2004	—	`conf`	Debugging Sequential Circuits Using Boolean Satisfiability. MTV Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith
2004	A	`conf`	Debugging sequential circuits using Boolean satisfiability. ICCAD Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
2004	—	`conf`	Design diagnosis using Boolean satisfiability. ASP-DAC Alexander Smith, Andreas G. Veneris, Anastasios Viglas
2004	—	`conf`	Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri
2004	J	`jnl`	Logic Rewiring for Delay and Power Minimization. J. Inf. Sci. Eng. Andreas G. Veneris
2004	A	`conf`	Managing Don't Cares in Boolean Satisfiability. DATE Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee
2003	—	`conf`	Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. MTV Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
2003	A	`conf`	Extraction Error Diagnosis and Correction in High-Performance Designs. ITC Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
2003	—	`conf`	Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. MTV Andreas G. Veneris
2003	—	`conf`	Logic verification based on diagnosis techniques. ASP-DAC Andreas G. Veneris, Alexander Smith, Magdy S. Abadir
2002	A	`conf`	Design Rewiring Using ATPG. ITC Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
2002	—	`conf`	Design rewiring for power minimization [logic design]. ISCAS (4) Mandana Amiri, Andreas G. Veneris, Ivor Ting
2002	J	`jnl`	Design rewiring using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas G. Veneris, Magdy S. Abadir
2002	—	`conf`	Efficient and Exact Diagnosis of Multiple Stuck-At Faults. LATW Jiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir
2002	A	`conf`	Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir
2002	A	`conf`	Incremental Diagnosis of Multiple Open-Interconnects. ITC Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi
2001	—	`conf`	ATPG Driven Logic Synthesis for Delay and Power Minimization. LATW Ivor Ting, Andreas G. Veneris, Magdy S. Abadir
2001	—	`conf`	Design rewiring based on diagnosis techniques. ASP-DAC Andreas G. Veneris, Magdy S. Abadir, Ivor Ting
2000	—	`conf`	Design Optimization Based on Diagnosis Techniques. LATW Andreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji
1999	—	`conf`	A hybrid approach to design error detection and correction [VLSI digital circuits]. ICECS Andreas G. Veneris, Ibrahim N. Hajj
1999	—	`conf`	Correcting multiple design errors in digital VLSI circuits. ISCAS (1) Andreas G. Veneris, Ibrahim N. Hajj
1999	J	`jnl`	Design error diagnosis and correction via test vector simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas G. Veneris, Ibrahim N. Hajj
1999	Misc	`conf`	Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. VTS Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs
1998	—	`—`	Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits Andreas G. Veneris
1997	—	`conf`	A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. Great Lakes Symposium on VLSI Andreas G. Veneris, Ibrahim N. Hajj
1995	J	`jnl`	Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. Acta Informatica Lefteris M. Kirousis, Andreas G. Veneris
1993	—	`conf`	Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. WDAG Lefteris M. Kirousis, Andreas G. Veneris