Andreas Dandalis

13 papers A 2B 5Misc 2Journal 3Unranked 1
YearRankTypeTitle / Venue / Authors
2005 J jnl
Configuration compression for FPGA-based embedded systems.
IEEE Trans. Very Large Scale Integr. Syst.
Andreas Dandalis, Viktor K. Prasanna
2004 J jnl
An adaptive cryptographic engine for internet protocol security architectures.
ACM Trans. Design Autom. Electr. Syst.
Andreas Dandalis, Viktor K. Prasanna
2002 J jnl
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers.
ACM Trans. Design Autom. Electr. Syst.
Andreas Dandalis, Viktor K. Prasanna
2001 A conf
Configuration compression for FPGA-based embedded systems.
FPGA
Andreas Dandalis, Viktor K. Prasanna
2001 B conf
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers.
FPL
Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam
2000 A conf
A Comparative Study of Performance of AES Final Candidates Using FPGAs.
CHES
Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
2000 B conf
A Parallel Pipelined SAT Solver for FPGAs.
FPL
Mark Redekopp, Andreas Dandalis
2000 Misc conf
An Adaptive Cryptographic Engine for IPSec Architectures.
FCCM
Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
2000 B conf
Efficient Self-Reconfigurable Implementations Using On-chip Memory.
FPL
Sameer Wadhwa, Andreas Dandalis
1999 — conf
Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices.
IPPS/SPDP Workshops
Andreas Dandalis, Alessandro Mei, Viktor K. Prasanna
1998 Misc conf
Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures.
FCCM
Andreas Dandalis, Viktor K. Prasanna
1998 B conf
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures.
FPL
Andreas Dandalis, Viktor K. Prasanna
1997 B conf
Fast parallel implementation of DFT using configurable devices.
FPL
Andreas Dandalis, Viktor K. Prasanna