Andreas Burg

265 papers A* 3A 8B 7C 31Misc 24Journal 103Unranked 88
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time.
IEEE J. Solid State Circuits
Odem Harel, Halil Andaç Yigit, Eliana Feifel, Robert Giterman, Andreas Burg, Adam Teman
2025 C conf
An SDR-Based Monostatic Wi-Fi System with Analog Self-Interference Cancellation for Sensing.
ISCAS
Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Andreas Burg
2025 B conf
Belief Propagation Decoding for Short Codes on Structured Sparse Parity-Check Matrices.
ISIT
Yifei Shen, Zongyao Li, Emmanuel Boutillon, Wenqing Song, Yuqing Ren, Chuan Zhang, Xiaohu You, Andreas Burg
2025 — conf
Dataset and UAV Propagation Channel Modeling for LoRa in the 860 MHz ISM Band.
IEEECONF
Joachim Tapparel, Andreas Burg
2025 J jnl
Device-Free Floor-Scale Human Detection With Indoor LTE Antennas.
IEEE Open J. Commun. Soc.
Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg
2025 — conf
Efficient Ordered Statistics Decoder with Unfolded Gaussian Elimination.
ISTC
Leyu Zhang, Yuqing Ren, Chuan Zhang, Andreas Burg, Yifei Shen
2025 B conf
Impact of Reactive Jamming Attacks on LoRaWAN: a Theoretical and Experimental Study.
PIMRC
Amavi Dossa, Andreas Burg, El Mehdi Amhoud
2025 — conf
Iterative Logistic Weight Based Chase Decoder for Open Forward Error Correction.
OFC
Yifei Shen, Wenqing Song, Ludovic Damien Blanc, Yuqing Ren, Alexios Balatsoukas-Stimming, Alex Alvarado, Andreas Burg
2025 J jnl
Toward Universal Belief Propagation Decoding for Short Binary Block Codes.
IEEE J. Sel. Areas Commun.
Yifei Shen, Zongyao Li, Yuqing Ren, Emmanuel Boutillon, Alexios Balatsoukas-Stimming, Chuan Zhang, Xiaohu You, Andreas Burg
2024 J jnl
A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuqing Ren, Hassan Harb, Yifei Shen, Alexios Balatsoukas-Stimming, Andreas Burg
2024 J jnl
A High Dynamic Range Envelop Detector for Heterodyne Receiver Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Naci Pekcokguler, Dominique Morche, Andreas Burg, Catherine Dehollain
2024 C conf
A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving.
ISCAS
Leyu Zhang, Yuqing Ren, Yifei Shen, Wuyang Zhou, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg
2024 J jnl
A Node-Based Polar List Decoder With Frame Interleaving and Ensemble Decoding Support.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuqing Ren, Leyu Zhang, Ludovic Damien Blanc, Yifei Shen, Xinwei Li, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg
2024 J jnl
A Node-Based Polar List Decoder with Frame Interleaving and Ensemble Decoding Support.
CoRR
Yuqing Ren, Leyu Zhang, Ludovic Damien Blanc, Yifei Shen, Xinwei Li, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg
2024 J jnl
Analytical Modeling of Short-Channel MOSFET Differential Pair Non-Linearity.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naci Pekcokguler, Hung-Chi Han, Dominique Morche, Catherine Dehollain, Andreas Burg, Christian C. Enz
2024 — conf
Centralized RAN for LPWAN: Architecture and Proof-of-Concept Prototype Implementation.
NFV-SDN
Joachim Tapparel, Andreas Burg
2024 J jnl
Edge-Spreading Raptor-Like LDPC Codes for 6G Wireless Systems.
CoRR
Yuqing Ren, Leyu Zhang, Yifei Shen, Wenqing Song, Emmanuel Boutillon, Alexios Balatsoukas-Stimming, Andreas Burg
2024 J jnl
High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes.
IEEE Trans. Signal Process.
Yuqing Ren, Yifei Shen, Leyu Zhang, Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Emmanuel Boutillon, Andreas Burg, Chuan Zhang
2024 B conf
Learning-based Hand Gesture Classification using Channel Impulse Response with UWB.
PIMRC
Clément Samanos, Han Miao, Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg
2024 — conf
LoRa Fine Synchronization with Two-Pass Time and Frequency Offset Estimation.
IEEECONF
Joachim Tapparel, Andreas Burg
2024 B conf
Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi.
WCNC
Andreas Toftegaard Kristensen, Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg
2024 — conf
Towards 6G: Configurable High-Throughput Decoder Implementation for SC-LDPC Codes.
IEEECONF
Yuqing Ren, Yifei Shen, Wenqing Song, Alexios Balatsoukas-Stimming, Emmanuel Boutillon, Andreas Burg
2023 J jnl
A High-Performance and Low-Complexity 5G LDPC Decoder: Algorithm and Implementation.
CoRR
Yuqing Ren, Hassan Harb, Yifei Shen, Alexios Balatsoukas-Stimming, Andreas Burg
2023 J jnl
An Ultra-Low-Power Widely-Tunable Complex Band-Pass Filter for RF Spectrum Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Naci Pekcokguler, Dominique Morche, Andreas Burg, Catherine Dehollain
2023 — conf
Band-of-Interest-Based Channel Impulse Response Fusion for Breathing Rate Estimation with UWB.
ICC Workshops
Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg
2023 — conf
Design of Concatenated Product Codes with Spatially-Coupled LDPC Codes.
ISWCS
Yuqing Ren, Yifei Shen, Emmanuel Boutillon, Alexios Balatsoukas-Stimming, Andreas Burg
2023 Misc conf
Improved Belief Propagation Decoding of Turbo Codes.
ICASSP
Yifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen, Xiaohu You, Chuan Zhang, Andreas Burg
2023 Misc conf
Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN.
ACSSC
Joachim Tapparel, Andreas Burg
2023 — conf
Iterative Ordered Statistics Decoding of Product Codes.
ISTC
Yifei Shen, Yuqing Ren, Andreas Burg
2023 — conf
LoRa Preamble Detection Robust to Inter-channel Interference.
SPAWC
Joachim Tapparel, Alexios Balatsoukas-Stimming, Andreas Burg
2023 — conf
Low Power LDPC Decoding by Reliable Voltage Down-Scaling.
NorCAS
Joonas Valkama, Mehdi Safarpour, Håkan Dicander, Zhongmin Deng, Andreas Burg, Olli Silvén
2023 Misc conf
Single-Anchor UWB Localization Using Channel Impulse Response Distributions.
ICASSP
Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg
2023 — conf
Spreading Factor assisted LoRa Localization with Deep Reinforcement Learning.
VTC2023-Spring
Yaya Etiabi, Mohammed Jouhari, Andreas Burg, El Mehdi Amhoud
2022 J jnl
A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation.
IEEE Internet Things J.
Mathieu Xhonneux, Joachim Tapparel, Alexios Balatsoukas-Stimming, Andreas Burg, Orion Afisiadis
2022 J jnl
A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation.
CoRR
Yuqing Ren, Andreas Toftegaard Kristensen, Yifei Shen, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg
2022 J jnl
A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation.
IEEE Trans. Signal Process.
Yuqing Ren, Andreas Toftegaard Kristensen, Yifei Shen, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg
2022 — conf
Beam Selection and Tracking for Amplify-and-Forward Repeaters.
VTC Spring
Adrian Schumacher, Ruben Merz, Andreas Burg
2022 J jnl
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness.
IEEE Des. Test
Reza Ghanaatian, Marco Widmer, Andreas Burg
2022 — conf
Device-free Movement Tracking using the UWB Channel Impulse Response with Machine Learning.
SPAWC
Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg
2022 J jnl
High-Throughput Flexible Belief Propagation List Decoder for Polar Codes.
CoRR
Yuqing Ren, Yifei Shen, Leyu Zhang, Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Andreas Burg, Chuan Zhang
2022 A conf
Increasing Cellular Network Energy Efficiency for Railway Corridors.
DATE
Adrian Schumacher, Ruben Merz, Andreas Burg
2022 J jnl
Increasing Cellular Network Energy Efficiency for Railway Corridors.
CoRR
Adrian Schumacher, Ruben Merz, Andreas Burg
2022 — conf
List Ordered Statistics Decoders for Polar Codes.
IEEECONF
Zongyao Li, Leyu Zhang, Yifei Shen, Andreas Burg, Xiaohu You, Chuan Zhang
2021 J jnl
3.5 GHz Coverage Assessment with a 5G Testbed.
CoRR
Adrian Schumacher, Ruben Merz, Andreas Burg
2021 — conf
A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System.
NEWCAS
Naci Pekcokguler, Mickael Maman, Andreas Burg, Catherine Dehollain, Dominique Morche
2021 — conf
A Two-User Successive Interference Cancellation LoRa Receiver with Soft-Decoding.
ACSCC
Mathieu Xhonneux, Joachim Tapparel, Péter Scheepers, Orion Afisiadis, Alexios Balatsoukas-Stimming, David Bol, Jérôme Louveaux, Andreas Burg
2021 J jnl
A mmWave Bridge Concept to Solve the Cellular Outdoor-to-Indoor Challenge.
CoRR
Adrian Schumacher, Ruben Merz, Andreas Burg
2021 J jnl
Adding Indoor Capacity Without Fiber Backhaul: A mmWave Bridge Prototype.
CoRR
Adrian Schumacher, Ruben Merz, Andreas Burg
2021 J jnl
Adding Indoor Capacity without Fiber Backhaul: An mmWave Bridge Prototype.
IEEE Commun. Mag.
Adrian Schumacher, Ruben Merz, Andreas Burg
2021 — conf
ComplexBeat: Breathing Rate Estimation from Complex CSI.
SiPS
Sitian Li, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming
2021 C conf
Dynamic Range and Complexity Optimization of Mixed-Signal Machine Learning Systems.
ISCAS
Naci Pekcokguler, Dominique Morche, Adrian Frischknecht, Christoph Gerum, Andreas Burg, Catherine Dehollain
2021 J jnl
E
IEEE Trans. Computers
Flavio Ponzina, Miguel Peón-Quirós, Andreas Burg, David Atienza
2021 J jnl
Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers.
IEEE Open J. Commun. Soc.
Joachim Tapparel, Mathieu Xhonneux, David Bol, Jérôme Louveaux, Andreas Burg
2021 — conf
Improving railway track coverage with mmWave bridges: A Measurement Campaign.
5G-MeMZ@SIGCOMM
Adrian Schumacher, Nima Jamaly, Ruben Merz, Andreas Burg
2021 — conf
Intrinsically Self-powered, Battery-free, and Sensor-free Ambient Light Control System.
IEEE SENSORS
Roberto La Rosa, Mario Costanza, Andreas Burg, Catherine Dehollain, Patrizia Livreri
2021 J jnl
On the Advantage of Coherent LoRa Detection in the Presence of Interference.
IEEE Internet Things J.
Orion Afisiadis, Sitian Li, Joachim Tapparel, Andreas Burg, Alexios Balatsoukas-Stimming
2021 J jnl
OpenCSI: An Open-Source Dataset for Indoor Localization Using CSI-Based Fingerprinting.
CoRR
Arthur Gassner, Claudiu Musat, Alexandru Rusu, Andreas Burg
2021 J jnl
Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding.
IEEE Trans. Veh. Technol.
Mohammad Rowshan, Andreas Burg, Emanuele Viterbo
2020 J jnl
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits
Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf
2020 Misc conf
A Maximum-Likelihood-based Multi-User LoRa Receiver Implemented in GNU Radio.
ACSSC
Mathieu Xhonneux, Joachim Tapparel, Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Burg
2020 — conf
A mmWave Bridge Concept to Solve the Cellular Outdoor-to-Indoor Challenge.
VTC Spring
Adrian Schumacher, Ruben Merz, Andreas Burg
2020 — conf
An Open-Source LoRa Physical Layer Prototype on GNU Radio.
SPAWC
Joachim Tapparel, Orion Afisiadis, Paul Mayoraz, Alexios Balatsoukas-Stimming, Andreas Burg
2020 J jnl
Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chuan Zhang, Yeong-Luh Ueng, Christoph Studer, Andreas Burg
2020 J jnl
Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chuan Zhang, Yeong-Luh Ueng, Christoph Studer, Andreas Burg
2020 — conf
Coded LoRa Frame Error Rate Analysis.
ICC
Orion Afisiadis, Andreas Burg, Alexios Balatsoukas-Stimming
2020 C conf
Complexity-efficient Fano Decoding of Polarization-adjusted Convolutional (PAC) Codes.
ISITA
Mohammad Rowshan, Andreas Burg, Emanuele Viterbo
2020 J jnl
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg
2020 J jnl
Design and Decoding of Irregular LDPC Codes Based on Discrete Message Passing.
IEEE Trans. Commun.
Michael Meidlinger, Gerald Matz, Andreas Burg
2020 C conf
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI.
ISCAS
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2020 C conf
Gain-Cell Embedded DRAMs: Modeling and Design Space.
ISCAS
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020 J jnl
Gain-Cell Embedded DRAMs: Modeling and Design Space.
IEEE Trans. Very Large Scale Integr. Syst.
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020 J jnl
Hardware Implementation of Neural Self-Interference Cancellation.
CoRR
Yann Kurzo, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming
2020 J jnl
Hardware Implementation of Neural Self-Interference Cancellation.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yann Kurzo, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming
2020 J jnl
Identification of Non-Linear RF Systems Using Backpropagation.
CoRR
Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming
2020 — conf
Identification of Non-Linear RF Systems using Backpropagation.
ICC Workshops
Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming
2020 J jnl
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.
IEEE Des. Test
Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón-Quirós, Davide Rossi, Andreas Burg, David Atienza
2020 Misc conf
Lupulus: A Flexible Hardware Accelerator for Neural Networks.
ICASSP
Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg
2020 J jnl
Lupulus: A Flexible Hardware Accelerator for Neural Networks.
CoRR
Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg
2020 — conf
Machine Learning Based Outdoor Localization using the RSSI of Multibeam Antennas.
SiPS
Ning Xu, Sitian Li, Clement Serge Charollais, Andreas Burg, Adrian Schumacher
2020 J jnl
On the Error Rate of the LoRa Modulation With Interference.
IEEE Trans. Wirel. Commun.
Orion Afisiadis, Matthieu Cotting, Andreas Burg, Alexios Balatsoukas-Stimming
2020 Misc conf
On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation.
ACSSC
Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Andreas Burg
2020 J jnl
Polarization-adjusted Convolutional (PAC) Codes: Fano Decoding vs List Decoding.
CoRR
Mohammad Rowshan, Andreas Burg, Emanuele Viterbo
2020 — conf
Training Channel Selection for Learning-Based 1-Bit Precoding in Massive MU-MIMO.
ICC Workshops
Sitian Li, Andreas Burg, Alexios Balatsoukas-Stimming
2019 — conf
3.5 GHz Coverage Assessment with a 5G Testbed.
VTC Spring
Adrian Schumacher, Ruben Merz, Andreas Burg
2019 — conf
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS.
CICC
Marc Pons, Christoph Thomas Müller, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi
2019 — conf
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
ISSCC
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019 — conf
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.
A-SSCC
Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici
2019 — conf
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
A-SSCC
Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019 Misc conf
Advanced Machine Learning Techniques for Self-Interference Cancellation in Full-Duplex Radios.
ACSSC
Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming
2019 J jnl
Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED).
IEEE Des. Test
Andreas Burg, Matthew M. Ziegler, Saibal Mukhopdhyay
2019 C conf
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space.
ISCAS
Ester Vicario Bravo, Andrea Bonetti, Andreas Burg
2019 J jnl
Editor's Note: Special Issue on Design and Implementation of Signal Processing Systems.
J. Signal Process. Syst.
Emmanuel Boutillon, Andreas Burg
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019 A* conf
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems.
DAC
Marco Widmer, Andrea Bonetti, Andreas Burg
2019 B conf
Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems.
PIMRC
Reza Ghanaatian, Vahid Jamali, Andreas Burg, Robert Schober
2019 J jnl
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. II Express Briefs
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2019 — conf
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS.
PRIME
Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici
2019 Misc conf
LoRa Symbol Error Rate Under Non-Aligned Interference.
ACSSC
Orion Afisiadis, Matthieu Cotting, Andreas Burg, Alexios Balatsoukas-Stimming
2019 J jnl
LoRa Symbol Error Rate Under Non-Chip- and Non-Phase-Aligned Interference.
CoRR
Orion Afisiadis, Matthieu Cotting, Andreas Burg, Alexios Balatsoukas-Stimming
2019 Misc conf
Lora Digital Receiver Analysis and Implementation.
ICASSP
Reza Ghanaatian, Orion Afisiadis, Matthieu Cotting, Andreas Burg
2019 — conf
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC.
PRIME
Christoph Thomas Müller, Marc Pons, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi
2018 J jnl
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap.
Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman
2018 J jnl
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing.
IEEE Trans. Very Large Scale Integr. Syst.
Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
2018 C conf
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI.
ISCAS
Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg
2018 J jnl
An 800-MHz Mixed- V
IEEE J. Solid State Circuits
Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
2018 J jnl
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
2018 Misc conf
Design and Implementation of a Neural Network Aided Self-Interference Cancellation Scheme for Full-Duplex Radios.
ACSSC
Yann Kurzo, Andreas Burg, Alexios Balatsoukas-Stimming
2018 — conf
Fast-SSC-flip decoding of polar codes.
WCNC Workshops
Pascal Giard, Andreas Burg
2018 J jnl
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel.
IEEE Trans. Commun.
Alexios Balatsoukas-Stimming, Andreas Burg
2018 J jnl
Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems.
CoRR
Reza Ghanaatian, Vahid Jamali, Andreas Burg, Robert Schober
2018 J jnl
LoRa Digital Receiver Analysis and Implementation.
CoRR
Reza Ghanaatian, Orion Afisiadis, Matthieu Cotting, Andreas Burg
2018 — conf
On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes.
ISTC
Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg
2018 J jnl
On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes.
CoRR
Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg
2018 J jnl
Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things.
Proc. IEEE
Andreas Burg, Anupam Chattopadhyay, Kwok-Yan Lam
2017 J jnl
A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing.
CoRR
Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
2017 J jnl
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test
Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
2017 — conf
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
ESSCIRC
Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
2017 J jnl
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems.
J. Signal Process. Syst.
Jeremy Constantin, Raphaël Houlmann, Nicholas Preyss, Nino Walenta, Hugo Zbinden, Pascal Junod, Andreas Burg
2017 J jnl
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.
ACM Trans. Design Autom. Electr. Syst.
Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg
2017 J jnl
Blind Detection of Polar Codes.
CoRR
Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg
2017 — conf
Blind detection of polar codes.
SiPS
Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg
2017 — conf
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.
WCNC Workshops
Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg
2017 J jnl
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.
CoRR
Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg
2017 — conf
DVFS based power management for LDPC decoders with early termination.
SiPS
Reza Ghanaatian, Andreas Burg
2017 — conf
Digital predistortion of hardware impairments for full-duplex transceivers.
GlobalSIP
Andrew Charles Mallory Austin, Orion Afisiadis, Andreas Burg
2017 J jnl
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017 J jnl
Fast-SSC-Flip Decoding of Polar Codes.
CoRR
Pascal Giard, Andreas Burg
2017 Misc conf
Full-duplex communications for wireless links with asymmetric capacity requirements.
ACSSC
Orion Afisiadis, Andrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Burg
2017 J jnl
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg
2017 J jnl
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
CoRR
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
2017 J jnl
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
2016 — conf
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
COOL Chips
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016 — conf
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.
ESSCIRC
Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
2016 C conf
A low-power correlator for wakeup receivers with algorithm pruning through early termination.
ISCAS
Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman, Andreas Burg
2016 C conf
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
ISCAS
Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
2016 J jnl
Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems.
J. Signal Process. Syst.
Christian Senning, Georgios Karakonstantis, Andreas Burg
2016 — conf
Design considerations on sliding-block viterbi detectors for high-speed data transmission.
ICSPCS
Hazar Yueksel, Giovanni Cherubini, Roy D. Cideciyan, Andreas Burg, Thomas Toifl
2016 — conf
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
ESSCIRC
Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg
2016 A conf
Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices.
DATE
Loris Duch, Pablo García Del Valle, Shrikanth Ganapathy, Andreas Burg, David Atienza
2016 — conf
Experimental signal-quality characterization of a high-capacity mmWave link for backhaul applications.
SAM
Nicholas Preyss, Andreas Burg
2016 J jnl
Hardware Decoders for Polar Codes: An Overview.
CoRR
Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross
2016 — conf
High-speed link with trellis-coded modulation and Reed-Solomon coding.
CSCN
Hazar Yueksel, Giovanni Cherubini, Roy D. Cideciyan, Simeon Furrer, Andreas Burg, Thomas Toifl
2016 J jnl
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst.
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
2016 J jnl
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish
2016 J jnl
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish
2016 — conf
Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency.
VTC Spring
Orion Afisiadis, Andrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Burg
2016 J jnl
Spatial Multiplexing of QPSK Signals with a Single Radio: Antenna Design and Over-the-Air Experiments.
CoRR
Mohsen Yousefbeiki, Andrew Charles Mallory Austin, Juan R. Mosig, Andreas Burg, Julien Perruisseau-Carrier
2016 J jnl
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues
2015 — conf
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm.
A-SSCC
Nicholas Preyss, Christian Senning, Andreas Burg, Wei-Chang Liu, Chun-Yi Liu, Shyh-Jye Jou
2015 — conf
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.
ESSCIRC
Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl
2015 — conf
A fully-unrolled LDPC decoder based on quantized message passing.
SiPS
Alexios Balatsoukas-Stimming, Michael Meidlinger, Reza Ghanaatian, Gerald Matz, Andreas Burg
2015 — conf
An FPGA-based accelerator for rapid simulation of SC decoding of polar codes.
ICECS
Johannes Wüthrich, Alexios Balatsoukas-Stimming, Andreas Burg
2015 C conf
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop.
ISCAS
Andrea Bonetti, Adam Teman, Andreas Burg
2015 — conf
Approximate computing with unreliable dynamic memories.
NEWCAS
Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis
2015 J jnl
Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression.
EURASIP J. Wirel. Commun. Netw.
Alexios Balatsoukas-Stimming, Andrew Charles Mallory Austin, Pavle Belanovic, Andreas Burg
2015 — conf
Channel shortening and equalization based on information rate maximization for evolved GSM/EDGE.
SiPS
Harald Kröll, Stefan Altorfer, Thomas Willi, Andreas Burg, Qiuting Huang
2015 J jnl
Cross-layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems.
CoRR
Christian Senning, Georgios Karakonstantis, Andreas Burg
2015 — conf
Digital synchronization for symbol-spaced IEEE802.11ad Gigabit mmWave systems.
ICECS
Nicholas Preyss, Andreas Burg
2015 Misc conf
Energy-proportional single-carrier frequency domain equalization for mmWave wireless communication.
ACSSC
Nicholas Preyss, Sara Rodriguez Egea, Andreas Burg
2015 J jnl
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs.
ACM Trans. Embed. Comput. Syst.
Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2015 A conf
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
DATE
Jeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay, Andreas Burg
2015 J jnl
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel.
CoRR
Alexios Balatsoukas-Stimming, Andreas Burg
2015 — conf
Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication.
MWSCAS
Nicholas Preyss, Lorenz Koestler, Andreas Burg
2015 A* conf
Mitigating the impact of faults in unreliable memories for error-resilient applications.
DAC
Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg
2015 C conf
On metric sorting for successive cancellation list decoding of polar codes.
ISCAS
Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg
2015 Misc conf
Quantized message passing for LDPC codes.
ACSSC
Michael Meidlinger, Alexios Balatsoukas-Stimming, Andreas Burg, Gerald Matz
2015 Misc conf
The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes.
ACSSC
Jiandong Mu, Aida Vosoughi, João Andrade, Alexios Balatsoukas-Stimming, Georgios Karakonstantis, Andreas Burg, Gabriel Falcão, Vítor Manuel Mendes da Silva, Joseph R. Cavallaro
2014 — conf
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI.
ISSCC
Matthew Weiner, Milovan Blagojevic, Sergey Skotnikov, Andreas Burg, Philippe Flatresse, Borivoje Nikolic
2014 C conf
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
ISCAS
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish
2014 J jnl
A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s.
IEEE Trans. Circuits Syst. I Regul. Pap.
Christian Senning, Lukas Bruderer, Josua Hunziker, Andreas Burg
2014 J jnl
A Signal Processor for Gaussian Message Passing.
CoRR
Harald Kröll, Stefan Zwicky, Reto Odermatt, Lukas Bruderer, Andreas Burg, Qiuting Huang
2014 Misc conf
A low-complexity improved successive cancellation decoder for polar codes.
ACSSC
Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Burg
2014 A conf
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability.
DATE
Georgios Karakonstantis, Aviinaash Sankaranarayanan, Mohamed M. Sabry, David Atienza, Andreas Burg
2014 C conf
A signal processor for Gaussian message passing.
ISCAS
Harald Kroll, Stefan Zwicky, Reto Odermatt, Lukas Bruderer, Andreas Burg, Qiuting Huang
2014 J jnl
Baseband and RF Hardware Impairments in Full-Duplex Wireless Systems: Experimental Characterisation and Suppression.
CoRR
Alexios Balatsoukas-Stimming, Andrew Charles Mallory Austin, Pavle Belanovic, Andreas Burg
2014 Misc conf
Cross layer energy-efficiency optimization for cognitive radio transceivers.
ICASSP
Christian Senning, Mikel Mendicute, Andreas Burg
2014 — conf
Data compression via logic synthesis.
ASP-DAC
Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli
2014 J jnl
Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage.
CoRR
Alexios Balatsoukas-Stimming, Andreas Burg
2014 J jnl
Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage.
IEEE Commun. Lett.
Alexios Balatsoukas-Stimming, Andreas Burg
2014 B conf
Enabling complexity-performance trade-offs for successive cancellation decoding of polar codes.
ISIT
Alexios Balatsoukas-Stimming, Georgios Karakonstantis, Andreas Burg
2014 J jnl
Energy Efficiency through Significance-Based Computing.
Computer
Dimitrios S. Nikolopoulos, Hans Vandierendonck, Nikolaos Bellas, Christos D. Antonopoulos, Spyros Lalis, Georgios Karakonstantis, Andreas Burg, Uwe Naumann
2014 B conf
FPGA implementation of an interior point method for high-speed model predictive control.
FPL
Junyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides
2014 J jnl
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel.
CoRR
Alexios Balatsoukas-Stimming, Andreas Burg
2014 C conf
Faulty successive cancellation decoding of polar codes for the binary erasure channel.
ISITA
Alexios Balatsoukas-Stimming, Andreas Burg
2014 J jnl
Hardware Architecture for List Successive Cancellation Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Alexios Balatsoukas-Stimming, Alexandre J. Raymond, Warren J. Gross, Andreas Burg
2014 J jnl
LLR-based Successive Cancellation List Decoding of Polar Codes.
CoRR
Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg
2014 Misc conf
LLR-based successive cancellation list decoding of polar codes.
ICASSP
Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg
2014 — conf
Measurement-based characterization of residual self-interference on a full-duplex MIMO testbed.
SAM
Konstantinos Alexandris, Alexios Balatsoukas-Stimming, Andreas Burg
2014 Misc conf
On the performance of LDPC and turbo decoder architectures with unreliable memories.
ACSSC
João Andrade, Aida Vosoughi, Guohui Wang, Georgios Karakonstantis, Andreas Burg, Gabriel Falcão, Vítor Manuel Mendes da Silva, Joseph R. Cavallaro
2014 J jnl
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM.
IEEE Trans. Circuits Syst. II Express Briefs
Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg
2014 Misc conf
Robust asynchronous indoor localization using LED lighting.
ICASSP
Georg Kail, Patrick Maechler, Nicholas Preyss, Andreas Burg
2014 Misc conf
Statistical data correction for unreliable memories.
ACSSC
Christoph Roth, Christoph Studer, Georgios Karakonstantis, Andreas Burg
2013 — conf
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
NEWCAS
Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli
2013 — conf
A multipurpose testbed for full-duplex wireless communications.
ICECS
Pavle Belanovic, Alexios Balatsoukas-Stimming, Andreas Burg
2013 — conf
A parallelized layered QC-LDPC decoder for IEEE 802.11ad.
NEWCAS
Alexios Balatsoukas-Stimming, Nicholas Preyss, Alessandro Cevrero, Andreas Burg, Christoph Roth
2013 — conf
Block-floating-point enhanced MMSE filter matrix computation for MIMO-OFDM communication systems.
ICECS
Christian Senning, Andreas Burg
2013 Misc conf
Channel-optimized vector quantization with mutual information as fidelity criterion.
ACSSC
Andreas Winkelbauer, Gerald Matz, Andreas Burg
2013 — conf
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS.
ESSCIRC
Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues
2013 Misc conf
Efficient vlsi implementation of reduced-state sequence estimation for wireless communications.
ICASSP
Stefan Zwicky, Christian Benkeser, Andreas Burg, Qiuting Huang
2013 J jnl
Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes.
CoRR
Alexios Balatsoukas-Stimming, Georgios Karakonstantis, Andreas Burg
2013 A conf
Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
DATE
Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis
2013 — conf
FireBird: PowerPC e200 based SoC for high temperature operation.
CICC
Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici
2013 C conf
Live demonstration: Real-time audio restoration using sparse signal recovery.
ISCAS
David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
2013 Misc conf
On self-interference suppression methods for low-complexity full-duplex MIMO.
ACSSC
Alexios Balatsoukas-Stimming, Pavle Belanovic, Konstantinos Alexandris, Andreas Burg
2013 A conf
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms.
DATE
Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza
2013 J jnl
Tree Search Architecture for List SC Decoding of Polar Codes
CoRR
Alexios Balatsoukas-Stimming, Andreas Burg
2013 — ed.
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
VLSI-SoC (Selected Papers)
Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis
2012 C ed.
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012
VLSI-SoC
Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis
2012 — conf
A 2.78 mm
ESSCIRC
Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Burg
2012 — conf
A novel constrained-Viterbi algorithm with linear equalization and grouping assistance.
ISWCS
Karim Badawi, Christian Benkeser, Christoph Roth, Qiuting Huang, Andreas Burg
2012 — conf
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.
VLSI-SoC (Selected Papers)
Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg
2012 J jnl
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.
IEEE Trans. Circuits Syst. Video Technol.
Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross
2012 J jnl
Data Mapping for Unreliable Memories
CoRR
Christoph Roth, Christian Benkeser, Christoph Studer, Georgios Karakonstantis, Andreas Burg
2012 — conf
Data mapping for unreliable memories.
Allerton Conference
Christoph Roth, Christian Benkeser, Christoph Studer, Georgios Karakonstantis, Andreas Burg
2012 — conf
Design of energy efficient and dependable health monitoring systems under unreliable nanometer technologies.
BODYNETS
Mohamed M. Sabry, Georgios Karakonstantis, David Atienza, Andreas Burg
2012 C conf
Hardware-efficient random sampling of fourier-sparse signals.
ISCAS
Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg
2012 — conf
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture.
ASAP
Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak
2012 J jnl
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture.
IACR Cryptol. ePrint Arch.
Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak
2012 — conf
Layered detection and decoding in MIMO wireless systems.
DASIP
Nicholas Preyss, Andreas Burg, Christoph Studer
2012 — conf
Low-complexity frequency synchronization for GSM systems: Algorithms and implementation.
ICUMT
Harald Kroll, Stefan Zwicky, Christian Benkeser, Qiuting Huang, Andreas Burg
2012 — conf
Low-complexity vector precoding for multi-user systems.
ACSCC
Maitane Barrenechea, Andreas Burg, Mikel Mendicute
2012 J jnl
Low-power processor architecture exploration for online biomedical signal analysis.
IET Circuits Devices Syst.
Ahmed Yasir Dogan, Jeremy Constantin, David Atienza, Andreas Burg, Luca Benini
2012 A conf
Multi-core architecture design for ultra-low-power wearable health monitoring systems.
DATE
Ahmed Yasir Dogan, Jeremy Constantin, Martino Ruggiero, Andreas Burg, David Atienza
2012 A* conf
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon.
DAC
Georgios Karakonstantis, Christoph Roth, Christian Benkeser, Andreas Burg
2012 — conf
Replica bit-line technique for embedded multilevel gain-cell DRAM.
NEWCAS
Muhammad Umer Khalid, Pascal Meinerzhagen, Andreas Burg
2012 — conf
Session MP8a1: MIMO communications and signal processing I.
ACSCC
Andreas Burg
2012 Misc conf
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
FCCM
Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2012 — conf
Sparsity-based real-time audio restoration.
DASIP
Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
2012 C conf
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture.
VLSI-SoC
Sandro Belfanti, Christian Benkeser, Karim Badawi, Qiuting Huang, Andreas Burg
2012 C conf
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.
VLSI-SoC
Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg
2012 J jnl
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk
2011 J jnl
An FPGA-based processing pipeline for high-definition stereo video.
EURASIP J. Image Video Process.
Pierre Greisen, Simon Heinzle, Markus H. Gross, Andreas Burg
2011 C conf
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
ISCAS
Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg
2011 J jnl
Computational stereo camera system with programmable control loop.
ACM Trans. Graph.
Simon Heinzle, Pierre Greisen, David Gallup, Christine Chen, Daniel Saner, Aljoscha Smolic, Andreas Burg, Wojciech Matusik, Markus H. Gross
2011 — conf
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.
PATMOS
Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini
2010 C conf
Area- and throughput-optimized VLSI architecture of sphere decoding.
VLSI-SoC
Markus Wenk, Lukas Bruderer, Andreas Burg, Christoph Studer
2010 J jnl
MIMO Transmission with Residual Transmit-RF Impairments
CoRR
Christoph Studer, Markus Wenk, Andreas Burg
2010 — conf
MIMO transmission with residual transmit-RF impairments.
WSA
Christoph Studer, Markus Wenk, Andreas Burg
2010 C conf
Matching pursuit: Evaluation and implementatio for LTE channel estimation.
ISCAS
Patrick Maechler, Pierre Greisen, Norbert Felber, Andreas Burg
2010 J jnl
Simulation and Emulation of MIMO Wireless Baseband Transceivers.
EURASIP J. Wirel. Commun. Netw.
Pierre Greisen, Simon Haene, Andreas Burg
2010 — conf
VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems.
VLSI-SoC (Selected Papers)
Christoph Studer, Markus Wenk, Andreas Burg
2010 C conf
VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection.
ISCAS
Lukas Bruderer, Christoph Studer, Markus Wenk, Dominik Seethaler, Andreas Burg
2009 J jnl
Design and Optimization of an HSDPA Turbo Decoder ASIC.
IEEE J. Solid State Circuits
Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang
2009 J jnl
Implementation of a 2×2 MIMO-OFDM receiver on an application specific processor.
Microelectron. J.
Stefan Eberli, Andreas Burg, Wolfgang Fichtner
2008 — conf
A 58mW 1.2mm
ISSCC
Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang
2008 J jnl
A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization.
IEEE J. Sel. Areas Commun.
Simon Haene, David Perels, Andreas Burg
2008 — conf
Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes.
ACSCC
Christoph Studer, Nicholas Preyss, Christoph Roth, Andreas Burg
2008 J jnl
Soft-output sphere decoding: algorithms and VLSI implementation.
IEEE J. Sel. Areas Commun.
Christoph Studer, Andreas Burg, Helmut Bölcskei
2007 — conf
Design of spatially multiplexed LDPC codes for multi-user detection.
EUSIPCO
Gottfried Lechner, Andreas Burg
2007 C conf
FFT Processor for OFDM Channel Estimation.
ISCAS
Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner
2007 — conf
Reduced-complexity mimo detector with close-to ml error rate performance.
ACM Great Lakes Symposium on VLSI
C. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner
2007 C conf
Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation.
ISCAS
Andreas Burg, Simon Haene, Wolfgang Fichtner, Markus Rupp
2007 C conf
VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition.
ISCAS
Peter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner
2007 C conf
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding.
ISCAS
Andreas Burg, Dominik Seethaler, Gerald Matz
2006 — conf
A Frame-Start Detector for a 4×4 MIMO-OFDM System.
ICASSP (4)
David Perels, Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner
2006 A conf
Advanced receiver algorithms for MIMO wireless communications.
DATE
Andreas Burg, Moritz Borgmann, Markus Wenk, Christoph Studer, Helmut Bölcskei
2006 C conf
Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems.
ISCAS
Andreas Burg, Simon Haene, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner
2006 C conf
K-best MIMO detection VLSI architectures achieving up to 424 Mbps.
ISCAS
Markus Wenk, Martin Zellweger, Andreas Burg, Norbert Felber, Wolfgang Fichtner
2006 C conf
Silicon implementation of an MMSE-based soft demapper for MIMO-BICM.
ISCAS
Simon Haene, Andreas Burg, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner
2005 J jnl
VLSI implementation of MIMO detection using the sphere decoding algorithm.
IEEE J. Solid State Circuits
Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger, Wolfgang Fichtner, Helmut Bölcskei
2004 — conf
A 2 Gb/s balanced AES crypto-chip implementation.
ACM Great Lakes Symposium on VLSI
Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin
2004 — conf
VLSI implementation of the sphere decoding algorithm.
ESSCIRC
Andreas Burg, Markus Wenk, Martin Zellweger, Marc Simon Wegmueller, Norbert Felber, Wolfgang Fichtner
2003 — conf
A 50 Mbps 4×4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation.
ICECS
Andreas Burg, Norbert Felber, Wolfgang Fichtner
2003 J jnl
Rapid prototyping for wireless designs: the five-ones approach.
Signal Process.
Markus Rupp, Andreas Burg, Eric C. Beck
2003 — conf
Variable delay ripple carry adder with carry chain interrupt detection.
ISCAS (5)
Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner