Andreas Becher

37 papers A 1B 4C 4Misc 1Journal 13Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Backing the Wrong Horse: How Bit-Level Netlist Augmentation can Counter Power Side Channel Attacks. CoRR Ali Asghar, Andreas Becher, Daniel Ziener
2024	J	`jnl`	Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
2024	—	`conf`	Short Paper: Analysis of Vivado implementation strategies regarding side-channel leakage for FPGA-based AES implementations. HASP@MICRO Ali Asghar, Andreas Becher, Daniel Ziener
2022	J	`jnl`	Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2022	—	`—`	Near-Data Query Processing on Heterogeneous FPGA-based Systems. Andreas Becher
2022	—	`conf`	Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	A	`conf`	Raw Filtering of JSON Data on FPGAs. DATE Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Raw Filtering of JSON Data on FPGAs. CoRR Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	B	`conf`	Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
2022	J	`jnl`	Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
2022	—	`conf`	Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener
2021	B	`conf`	Choice - A Tunable PUF-Design for FPGAs. FPL Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich
2021	J	`jnl`	On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2021	J	`jnl`	Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
2020	J	`jnl`	Query-Sequence Optimization on a Reconfigurable Hardware-Accelerated System. CoRR Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener
2020	B	`conf`	SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich
2020	—	`conf`	Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
2020	J	`jnl`	Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
2020	J	`jnl`	The ReProVide Query-Sequence Optimization in a Hardware-Accelerated DBMS. CoRR Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener
2020	C	`conf`	The ReProVide query-sequence optimization in a hardware-accelerated DBMS. DaMoN Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Klaus Meyer-Wegener
2019	—	`conf`	Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich
2019	C	`conf`	In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. DaMoN Andreas Becher, Jürgen Teich
2019	—	`conf`	ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich
2018	—	`conf`	Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich
2018	J	`jnl`	Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann
2018	—	`conf`	Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich
2018	C	`conf`	Optimistic regular expression matching on FPGAs for near-data processing. DaMoN Andreas Becher, Stefan Wildermann, Jürgen Teich
2017	C	`conf`	Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann
2016	Misc	`conf`	A LUT-Based Approximate Adder. FCCM Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich
2016	—	`conf`	FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener
2016	J	`jnl`	FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
2016	—	`conf`	Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann
2016	—	`conf`	ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich
2015	—	`conf`	A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich
2015	—	`conf`	Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger
2014	B	`conf`	Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich