Andrea Pugliese

17 papers C 1Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2012 J jnl
A new efficient SC integrator scheme for high-speed low-power applications.
Int. J. Circuit Theory Appl.
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
2012 J jnl
Design approach for high-bandwidth low-power three-stage operational amplifiers.
Int. J. Circuit Theory Appl.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2011 J jnl
Design criterion for high-speed low-power SC circuits.
Int. J. Circuit Theory Appl.
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
2010 J jnl
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance.
Microelectron. J.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2010 J jnl
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2010 J jnl
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2009 — conf
Class-AB output stage design for high-speed three-stage op-amps.
ICECS
Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese
2009 — conf
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers.
ICECS
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
2009 C conf
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.
ISCAS
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2009 J jnl
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2008 J jnl
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2008 — conf
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
PATMOS
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2007 — conf
Design methodology of nested-Miller amplifiers for small capacitive loads.
ECCTD
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2007 — conf
Settling Time Minimization of Operational Amplifiers.
PATMOS
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2006 — conf
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
PATMOS
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2006 — conf
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
PATMOS
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2005 — conf
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
PATMOS
Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo