| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2012 | J | jnl |
Int. J. Circuit Theory Appl.
|
| 2012 | J | jnl |
Int. J. Circuit Theory Appl.
|
| 2011 | J | jnl |
Int. J. Circuit Theory Appl.
|
| 2010 | J | jnl |
Microelectron. J.
|
| 2010 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2010 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2009 | — | conf |
ICECS
|
| 2009 | — | conf |
ICECS
|
| 2009 | C | conf |
ISCAS
|
| 2009 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2008 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2008 | — | conf |
PATMOS
|
| 2007 | — | conf |
ECCTD
|
| 2007 | — | conf |
PATMOS
|
| 2006 | — | conf |
PATMOS
|
| 2006 | — | conf |
PATMOS
|
| 2005 | — | conf |
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
PATMOS
|