Andrea Calimera

144 papers A* 3A 23B 2C 21Misc 1Journal 47Unranked 45

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Refined Two-Sided Learning Rate Tuning for Robust Evaluation in Federated Learning. IEEE Trans. Artif. Intell. Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
2025	—	`conf`	Adaptive Client Participation in Budget-Constrained Federated Learning with Extreme Label Skew. NewCAS Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
2025	B	`conf`	Gradient-Aware Participation for Energy Reduction in Federated Learning with Extreme Label Skew. IJCNN Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
2025	B	`conf`	Privacy-Preserving Federated Learning for Household Characteristic Identification. COMPSAC Erich Malan, Claudia De Vizia, Marco Castangia, Valentino Peluso, Andrea Calimera, Enrico Macii
2024	J	`jnl`	Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning. IEEE Internet Things J. Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii, Paolo Montuschi
2024	C	`conf`	Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption. ICCD Valentino Peluso, Erich Malan, Andrea Calimera, Enrico Macii
2023	J	`jnl`	Communication-Efficient Federated Learning With Gradual Layer Freezing. IEEE Embed. Syst. Lett. Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
2023	—	`conf`	Concurrent Pipeline Stages Optimization for Embedded Keyword Spotting. AIIoT Giacomo Zema, Valentino Peluso, Andrea Calimera, Enrico Macii
2023	J	`jnl`	Dynamic ConvNets on Tiny Devices via Nested Sparsity. IEEE Internet Things J. Matteo Grimaldi, Luca Mocerino, Antonio Cipolletta, Andrea Calimera
2023	J	`jnl`	Efficient Deep Learning Models for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays. IEEE Internet Things J. Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2023	J	`jnl`	Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays. CoRR Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2023	A	`conf`	Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. ISLPED Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
2023	J	`jnl`	Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference. Sensors Chen Xie, Alessio Burrello, Francesco Daghero, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2022	J	`jnl`	Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. CoRR Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2022	J	`jnl`	Dynamic ConvNets on Tiny Devices via Nested Sparsity. CoRR Matteo Grimaldi, Luca Mocerino, Antonio Cipolletta, Andrea Calimera
2022	J	`jnl`	Editorial: Language and Vision in Robotics: Emerging Neural and On-Device Approaches. Frontiers Comput. Sci. Giovanni Luca Masala, Massimo Esposito, Umberto Maniscalco, Andrea Calimera
2022	J	`jnl`	Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs. IEEE Internet Things J. Antonio Cipolletta, Valentino Peluso, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
2022	—	`conf`	Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference. PRIME Chen Xie, Daniele Jahier Pagliari, Andrea Calimera
2022	J	`jnl`	Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference. CoRR Chen Xie, Daniele Jahier Pagliari, Andrea Calimera
2022	J	`jnl`	Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. CoRR Francesco Daghero, Alessio Burrello, Chen Xie, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2022	J	`jnl`	Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. ACM Trans. Embed. Comput. Syst. Francesco Daghero, Alessio Burrello, Chen Xie, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2022	J	`jnl`	Monocular Depth Perception on Microcontrollers for Edge Applications. IEEE Trans. Circuits Syst. Video Technol. Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
2022	C	`conf`	Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. ISCAS Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2022	J	`jnl`	Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. CoRR Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2022	—	`conf`	SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing. LATS Khaled Sidahmed Sidahmed Alamin, Yukai Chen, Sebastiano Gaiardelli, Stefano Spellini, Andrea Calimera, Alessandro Beghi, Gian Antonio Susto, Franco Fummi, Enrico Macii, Sara Vinco
2022	J	`jnl`	Ultra-compact Binary Neural Networks for Human Activity Recognition on RISC-V Processors. CoRR Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino
2022	—	`ed.`	VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Victor Grimblatt, Chip-Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera
2021	A	`conf`	ACME: An Energy-Efficient Approximate Bus Encoding for I ISLPED Chen Xie, Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino
2021	C	`conf`	AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. VLSI-SoC Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
2021	C	`conf`	Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. VLSI-SoC Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2021	J	`jnl`	Adaptive Test-Time Augmentation for Low-Power CPU. CoRR Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
2021	A	`conf`	Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks. DATE Antonio Cipolletta, Andrea Calimera
2021	J	`jnl`	Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net). IEEE Trans. Circuits Syst. I Regul. Pap. Luca Mocerino, Andrea Calimera
2021	—	`conf`	Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers. VLSI-SoC (Selected Papers) Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
2021	J	`jnl`	Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools. Proc. IEEE Tania Cerquitelli, Daniele Jahier Pagliari, Andrea Calimera, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Massimo Poncino
2021	A*	`conf`	On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage. DAC Antonio Cipolletta, Andrea Calimera
2021	—	`conf`	On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets. VLSI-SoC (Selected Papers) Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
2021	J	`jnl`	TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets. IEEE Trans. Circuits Syst. II Express Briefs Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera
2021	—	`conf`	Ultra-compact binary neural networks for human activity recognition on RISC-V processors. CF Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino
2021	—	`ed.`	VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
2020	J	`jnl`	Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231]. Integr. Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou
2020	—	`conf`	EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. AICAS Matteo Grimaldi, Valentino Peluso, Andrea Calimera
2020	—	`conf`	Enabling monocular depth perception at the very edge. CVPR Workshops Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
2020	J	`jnl`	Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2020	C	`conf`	Optimization Tools for ConvNets on the Edge. VLSI-SOC Valentino Peluso, Enrico Macii, Andrea Calimera
2020	—	`conf`	TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. AICAS Luca Mocerino, Andrea Calimera
2019	C	`conf`	Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. VLSI-SoC Valentino Peluso, Matteo Grimaldi, Andrea Calimera
2019	—	`conf`	CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. ICECS Luca Mocerino, Andrea Calimera
2019	J	`jnl`	CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. CoRR Luca Mocerino, Andrea Calimera
2019	J	`jnl`	EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. CoRR Matteo Grimaldi, Valentino Peluso, Andrea Calimera
2019	A	`conf`	Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. DATE Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia
2019	A	`conf`	Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. DATE Luca Mocerino, Valerio Tenace, Andrea Calimera
2019	—	`conf`	Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets. SNAMS Valentino Peluso, Roberto Giorgio Rizzo, Antonio Cipolletta, Andrea Calimera
2019	—	`conf`	Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores. ICECS Valentino Peluso, Antonio Cipolletta, Francesco Vaiana, Andrea Calimera
2019	J	`jnl`	Layer-Wise Compressive Training for Convolutional Neural Networks. Future Internet Matteo Grimaldi, Valerio Tenace, Andrea Calimera
2019	J	`jnl`	Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores. IEEE Access Matteo Grimaldi, Valentino Peluso, Andrea Calimera
2019	A	`conf`	SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. DATE Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera
2019	J	`jnl`	TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. CoRR Luca Mocerino, Andrea Calimera
2018	—	`conf`	A compression-driven training framework for embedded deep neural networks. INTESA@ESWEEK Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera
2018	A	`conf`	All-digital embedded meters for on-line power estimation. DATE Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino
2018	J	`jnl`	Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling. Integr. Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou
2018	C	`conf`	Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
2018	—	`conf`	Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. VLSI-SoC (Selected Papers) Valentino Peluso, Andrea Calimera
2018	C	`conf`	Energy-Driven Precision Scaling for Fixed-Point ConvNets. VLSI-SoC Valentino Peluso, Andrea Calimera
2018	A	`conf`	Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
2018	C	`conf`	Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. VLSI-SoC Valerio Tenace, Andrea Calimera
2018	—	`conf`	Logic-In-Memory Architecture For Min/Max Search. ICECS Marco Vacca, Yaswanth Tavva, Anupam Chattopadhyay, Andrea Calimera
2018	C	`conf`	Multiplication by Inference using Classification Trees: A Case-Study Analysis. ISCAS Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera
2018	J	`jnl`	Quasi-exact logic functions through classification trees. Integr. Valerio Tenace, Andrea Calimera
2018	A	`conf`	Scalable-effort ConvNets for multilevel classification. ICCAD Valentino Peluso, Andrea Calimera
2018	C	`conf`	Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. ISCAS Valentino Peluso, Andrea Calimera
2017	—	`conf`	Activation-Kernel Extraction through Machine Learning. NGCAS Valerio Tenace, Andrea Calimera
2017	C	`conf`	Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. VLSI-SoC Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou, Xin Liu
2017	—	`conf`	On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling. VLSI-SoC (Selected Papers) Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou
2017	—	`conf`	Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling. NGCAS Roberto Giorgio Rizzo, Andrea Calimera
2016	—	`conf`	Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. VLSI-SoC (Selected Papers) Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto
2016	C	`conf`	Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	—	`conf`	Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	—	`conf`	Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	C	`conf`	Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	J	`jnl`	Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	C	`conf`	Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. VLSI-SoC Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto
2015	C	`conf`	An automated design flow for approximate circuits based on reduced precision redundancy. ICCD Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	—	`conf`	Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. ACM Great Lakes Symposium on VLSI Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	—	`conf`	Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. ACM Great Lakes Symposium on VLSI Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	Misc	`conf`	Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. VLSID Felipe Lavratti, Letícia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera, Enrico Macii
2015	—	`conf`	Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2015	A*	`conf`	One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	J	`jnl`	Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	J	`jnl`	Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino
2014	J	`jnl`	Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	A	`conf`	Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	J	`jnl`	Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2014	C	`conf`	Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. DSD Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	A	`conf`	A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. DATE Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	—	`conf`	Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	A*	`conf`	Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. DAC Andrea Calimera, Enrico Macii, Massimo Poncino
2013	—	`conf`	Exploration of different implementation styles for graphene-based reconfigurable gates. ICICDT Sandeep Miryala, Andrea Calimera, Massimo Poncino, Enrico Macii
2013	—	`conf`	Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Letícia Maria Veiras Bolzani Poehls
2013	J	`jnl`	Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino
2013	J	`jnl`	Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. Microelectron. J. Alessandro Sassone, Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2013	—	`conf`	Power modeling and characterization of Graphene-based logic gates. PATMOS Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	—	`conf`	Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. LATW Felipe Lavratti, Letícia Maria Veiras Bolzani, Andrea Calimera, Fabian Vargas, Enrico Macii
2012	J	`jnl`	Design Techniques and Architectures for Low-Leakage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2012	J	`jnl`	Design Techniques for NBTI-Tolerant Power-Gating Architectures. IEEE Trans. Circuits Syst. II Express Briefs Andrea Calimera, Enrico Macii, Massimo Poncino
2012	A	`conf`	Energy-optimal caches with guaranteed lifetime. ISLPED Mirko Loghi, Haroon Mahmood, Andrea Calimera, Massimo Poncino, Enrico Macii
2012	A	`conf`	IR-drop analysis of graphene-based power distribution networks. DATE Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2012	A	`conf`	Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. DATE Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Richard Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo
2012	—	`conf`	NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2012	J	`jnl`	NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electron. Test. Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
2012	—	`conf`	On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. PATMOS Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2012	J	`jnl`	On-chip process variation-tracking through an all-digital monitoring architecture. IET Circuits Devices Syst. Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2011	—	`conf`	A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs. LATW Felipe Lavratti, Andrea Calimera, Letícia Maria Veiras Bolzani, Fabian Vargas, Enrico Macii
2011	—	`conf`	An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. PATMOS Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2011	—	`conf`	Buffering of frequent accesses for reduced cache aging. ACM Great Lakes Symposium on VLSI Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino
2011	A	`conf`	Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. DATE Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino
2011	—	`conf`	NBTI-aware data allocation strategies for scratchpad memory based embedded systems. LATW Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
2011	A	`conf`	Partitioned cache architectures for reduced NBTI-induced aging. DATE Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino
2011	J	`jnl`	Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. IEEE J. Emerg. Sel. Topics Circuits Syst. Leandro Max de Lima Silva, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2011	—	`conf`	Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2010	—	`conf`	Aging effects of leakage optimizations for caches. ACM Great Lakes Symposium on VLSI Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino
2010	—	`conf`	An integrated thermal estimation framework for industrial embedded platforms. ACM Great Lakes Symposium on VLSI Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella
2010	C	`conf`	Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. ISCAS Andrea Calimera, Enrico Macii, Massimo Poncino
2010	J	`jnl`	Dual-V Microelectron. J. Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
2010	A	`conf`	Dynamic indexing: concurrent leakage and aging optimization for caches. ISLPED Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino
2010	—	`conf`	Generating power-hungry test programs for power-aware validation of pipelined processors. SBCCI Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda
2010	J	`jnl`	NBTI-Aware Clustered Power Gating. ACM Trans. Design Autom. Electr. Syst. Andrea Calimera, Enrico Macii, Massimo Poncino
2010	A	`conf`	Post-placement temperature reduction techniques. DATE Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino
2010	J	`jnl`	Temperature-Insensitive Dual- V IEEE Trans. Very Large Scale Integr. Syst. Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
2009	J	`jnl`	Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2009	A	`conf`	Enabling concurrent clock and power gating in an industrial design flow. DATE Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2009	A	`conf`	NBTI-aware power gating for concurrent leakage and aging optimization. ISLPED Andrea Calimera, Enrico Macii, Massimo Poncino
2009	—	`conf`	NBTI-aware sleep transistor design for reliable power-gating. ACM Great Lakes Symposium on VLSI Andrea Calimera, Enrico Macii, Massimo Poncino
2009	—	`conf`	On-chip Thermal Modeling Based on SPICE Simulation. PATMOS Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino
2009	C	`conf`	Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2009	—	`conf`	Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. PATMOS Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2008	C	`conf`	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino
2008	C	`conf`	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2008	A	`conf`	Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. DATE Andrea Calimera, Luca Benini, Enrico Macii
2008	A	`conf`	Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
2008	—	`conf`	Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar
2008	J	`jnl`	Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino
2007	—	`conf`	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2007	A	`conf`	Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino