Andrea Bonetti

32 papers A* 1A 1C 6Journal 16Unranked 8
YearRankTypeTitle / Venue / Authors
2025 — conf
GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification.
MLCAD
Phuoc Pham, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Stefan Uhlich, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann, Robert Wille
2025 J jnl
GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification.
CoRR
Phuoc Pham, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Stefan Uhlich, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann, Robert Wille
2025 J jnl
Locality-aware Surrogates for Gradient-based Black-box Optimization.
CoRR
Ali Momeni, Stefan Uhlich, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Ryoga Matsuo, Eisaku Ohbuchi, Lorenzo Servadei
2025 — conf
Schemato - An LLM for Netlist-to-Schematic Conversion.
MLCAD
Ryoga Matsuo, Stefan Uhlich, Arun Venkitaraman, Andrea Bonetti, Chia-Yu Hsieh, Ali Momeni, Lukas Mauch, Augusto Capone, Eisaku Ohbuchi, Lorenzo Servadei
2025 J jnl
SpiceMixer - Netlist-Level Circuit Evolution.
CoRR
Stefan Uhlich, Andrea Bonetti, Arun Venkitaraman, Chia-Yu Hsieh, Mustafa Emre Gürsoy, Ryoga Matsuo, Lorenzo Servadei
2024 J jnl
GraCo - A Graph Composer for Integrated Circuits.
CoRR
Stefan Uhlich, Andrea Bonetti, Arun Venkitaraman, Ali Momeni, Ryoga Matsuo, Chia-Yu Hsieh, Eisaku Ohbuchi, Lorenzo Servadei
2024 J jnl
Schemato - An LLM for Netlist-to-Schematic Conversion.
CoRR
Ryoga Matsuo, Stefan Uhlich, Arun Venkitaraman, Andrea Bonetti, Chia-Yu Hsieh, Ali Momeni, Lukas Mauch, Augusto Capone, Eisaku Ohbuchi, Lorenzo Servadei
2022 J jnl
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
ACM Trans. Embed. Comput. Syst.
Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini
2021 J jnl
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
CoRR
Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini
2021 — conf
Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.
EMBC
Enric M. Calvo, Philippe Renevey, Mathieu Lemay, Andrea Bonetti, Marc Pons Solé, Régis Cattenoz, Stéphane Emery, Ricard Delgado-Gonzalo
2020 J jnl
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg
2020 C conf
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI.
ISCAS
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2020 C conf
Gain-Cell Embedded DRAMs: Modeling and Design Space.
ISCAS
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020 J jnl
Gain-Cell Embedded DRAMs: Modeling and Design Space.
IEEE Trans. Very Large Scale Integr. Syst.
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020 J jnl
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.
IEEE Des. Test
Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón-Quirós, Davide Rossi, Andreas Burg, David Atienza
2019 — conf
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.
A-SSCC
Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici
2019 C conf
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space.
ISCAS
Ester Vicario Bravo, Andrea Bonetti, Andreas Burg
2019 A* conf
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems.
DAC
Marco Widmer, Andrea Bonetti, Andreas Burg
2019 J jnl
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. II Express Briefs
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2018 C conf
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI.
ISCAS
Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg
2017 J jnl
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.
ACM Trans. Design Autom. Electr. Syst.
Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg
2017 J jnl
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg
2017 J jnl
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
CoRR
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
2017 J jnl
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg
2016 J jnl
An efficient tool for the assisted design of SAR ADCs capacitive DACs.
Integr.
Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
2016 — conf
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
ESSCIRC
Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg
2015 A conf
A tool for the assisted design of charge redistribution SAR ADCs.
DATE
Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
2015 C conf
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop.
ISCAS
Andrea Bonetti, Adam Teman, Andreas Burg
2015 — conf
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters.
NORCAS
Stefano Brenna, Luca Bettini, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
2015 C conf
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder.
ISCAS
Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg
2014 — conf
A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs.
UKSim
Stefano Brenna, Andrea Bonetti, Andrea L. Lacaita, Andrea Bonfanti
2014 — conf
A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs.
MIPRO
Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita