Andrea Bevilacqua

106 papers C 13Journal 43Unranked 49
YearRankTypeTitle / Venue / Authors
2026 J jnl
On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Bevilacqua, Andrea Mazzanti
2025 J jnl
A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS.
IEEE Solid State Circuits Lett.
Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua
2025 — conf
A DLL-Based FSK Demodulator for Asynchronous Communications.
PRIME
Lucrezia Navarin, Andrea Neviani, Andrea Bevilacqua
2025 — conf
A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking.
NewCAS
Luca Bellemo, Andrea Neviani, Andrea Bevilacqua
2025 J jnl
A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication.
IEEE Solid State Circuits Lett.
Lucrezia Navarin, Karl Norling, Marco Parenzan, Stefano Ruzzu, Andrea Neviani, Andrea Bevilacqua
2025 — conf
Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters.
ICICDT
Domenico Frassetto, Stefano Cabizza, Matteo Agostinelli, Cristian Garbossa, Giorgio Spiazzi, Andrea Bevilacqua, Andrea Neviani
2025 — conf
Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications.
PRIME
Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua
2025 — conf
Analysis of a gm-C Complex Filter for Low Power Wireless Receivers.
PRIME
Lorenzo Guglielmini, Andrea Bevilacqua
2025 J jnl
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst.
Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua
2024 J jnl
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies.
IEEE Trans. Circuits Syst. II Express Briefs
Lorenzo Tomasin, Agata Iesurum, Andrea Gobbo, Andrea Neviani, Andrea Bevilacqua
2024 J jnl
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs.
IEEE J. Solid State Circuits
Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
2024 J jnl
Analysis of CMRR in Doubly-Tuned Transformer Baluns.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bevilacqua, Andrea Mazzanti
2024 — conf
Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology.
PRIME
Nicolò Zugno, Andrea Bevilacqua
2024 J jnl
ELICIPY 1.0: A Python online tool for expert elicitation.
SoftwareX
Mattia de'Michieli Vitturi, Andrea Bevilacqua, Alessandro Tadini, Augusto Neri
2024 J jnl
On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband.
IEEE Trans. Circuits Syst. II Express Briefs
Luca Bellemo, Andrea Bevilacqua
2024 — conf
On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers.
NorCAS
Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua
2024 — conf
On the Efficiency of Output-Matched Radiofrequency Power Amplifiers.
PRIME
Davide Pecile, Stefan Kokorovic, Alberto Gambarucci, Andrea Bevilacqua
2024 — conf
On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting.
NorCAS
Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua
2023 J jnl
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
IEEE J. Solid State Circuits
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023 J jnl
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
2023 — conf
A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem.
PRIME
Lorenzo Tomasin, Andrea Bevilacqua
2023 — conf
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies.
PRIME
Nicolò Zugno, Francesco Brandonisio, Thomas Niederfriniger, Andrea Bevilacqua
2022 J jnl
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise.
IEEE J. Solid State Circuits
Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
2022 — conf
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS.
ESSCIRC
Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
2022 — conf
A 68.6fs
ISSCC
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2022 — conf
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.
CICC
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2022 J jnl
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications.
IEEE J. Solid State Circuits
Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
2022 J jnl
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.
IEEE J. Solid State Circuits
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2021 — conf
A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS.
ESSCIRC
Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
2021 J jnl
Doubly-Tuned Transformer Networks: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bevilacqua, Andrea Mazzanti
2021 — conf
Session 20 Overview: High-Performance VCOs Rf Subcommittee.
ISSCC
Andrea Bevilacqua, Salvatore Levantino, Hua Wang
2020 J jnl
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects.
IEEE J. Solid State Circuits
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
2020 J jnl
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO.
IEEE J. Solid State Circuits
Simone Veni, Pietro Andreani, Michele Caruso, Marc Tiebout, Andrea Bevilacqua
2020 C conf
Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters.
ISCAS
Gianluca Marin, Kyrylo Cherniak, Volha Subotskaya, Emanuele Bodano, Christoph Sandner, Andrea Bevilacqua
2019 — conf
A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS.
BCICTS
Andrea Bilato, Vadim Issakov, Andrea Bevilacqua
2019 — conf
A 130-nm CMOS Dual Input-Polarity DC-DC Converter for Low-Power Applications.
ESSCIRC
Alberto Gatti, Giorgio Spiazzi, Andrea Gerosa, Andrea Neviani, Andrea Bevilacqua
2019 — conf
A 17 GHz All-npn Push-Pull Class-C VCO.
BCICTS
Simone Veni, Michele Caruso, Marc Tiebout, Andrea Bevilacqua
2019 — conf
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion.
ESSCIRC
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua
2019 — conf
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS.
ESSCIRC
Matteo Bassi, Giovanni Boi, Fabio Padovan, Jonas Fritzin, Stefano Di Martino, Daniel Knauder, Andrea Bevilacqua
2019 C conf
A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology.
ISCAS
Andrea Gerosa, Andrea Bevilacqua, Giorgio Spiazzi
2019 — conf
Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters.
ICECS
Gianluca Marin, Kyrylo Cherniak, Volha Subotskaya, Emanuele Bodano, Christoph Sandner, Andrea Bevilacqua
2018 — conf
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm
ICECS
Antonio Passamani, Davide Ponton, Andreas Wolter, Gerhard Knoblinger, Andrea Bevilacqua
2018 — conf
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations.
ISSCC
Fabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua
2018 — conf
Analyzing Complex Models Using Data and Statistics.
ICCS (2)
Abani K. Patra, Andrea Bevilacqua, Ali Akhavan-Safaei
2018 J jnl
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Paolo Scaramuzza, Carlo Rubino, Michele Caruso, Marc Tiebout, Andrea Bevilacqua, Andrea Neviani
2018 J jnl
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits
Andrea Bevilacqua, Shidhartha Das, Pieter Harpe
2018 J jnl
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua
2018 J jnl
On the Remarkable Performance of the Series-Resonance CMOS Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Federico Pepe, Andrea Bevilacqua, Pietro Andreani
2018 J jnl
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Mazzanti, Andrea Bevilacqua
2018 — conf
Session 23 overview: LO generation: RF subcommittee.
ISSCC
Hyunchol Shin, Andrea Bevilacqua, Piet Wambacq
2017 — conf
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE.
ISSCC
Antonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani, Andrea Bevilacqua
2017 — conf
A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset.
ESSCIRC
Fabio Boscolo, Fabio Padovan, Fabio Quadrelli, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2017 — conf
Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems.
ESSCIRC
Paolo Scaramuzza, Carlo Rubino, Marc Tiebout, Michele Caruso, Markus Ortner, Andrea Neviani, Andrea Bevilacqua
2016 J jnl
A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation.
IEEE J. Solid State Circuits
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2016 — conf
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers.
ESSCIRC
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2016 J jnl
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita
2015 — conf
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation.
ESSCIRC
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
2015 J jnl
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani
2015 J jnl
A 40-67 GHz Power Amplifier With 13 dBm ℙ
IEEE J. Solid State Circuits
Matteo Bassi, Junlei Zhao, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto
2015 — conf
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs.
NORCAS
Antonio Passamani, Davide Ponton, Gerhard Knoblinger, Andrea Bevilacqua
2015 J jnl
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani
2015 J jnl
On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Mazzanti, Andrea Bevilacqua
2014 — conf
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS.
ESSCIRC
Fabio Padovan, Andrea Bevilacqua, Andrea Neviani
2014 — conf
A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP.
ESSCIRC
Junlei Zhao, Matteo Bassi, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto
2014 — conf
Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications.
ICECS
Andrea Bevilacqua, Andrea Neviani
2013 — conf
A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS.
ISSCC
Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani
2013 J jnl
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer.
IEEE J. Solid State Circuits
Matteo Bassi, Michele Caruso, Andrea Bevilacqua, Andrea Neviani
2013 — conf
Wideband 2-16GHz local oscillator generation for short-range radar applications.
ESSCIRC
Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani
2012 — conf
A 1.75-15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS.
ESSCIRC
Matteo Bassi, Michele Caruso, Andrea Bevilacqua, Andrea Neviani
2012 — conf
A SiGe bipolar VCO for backhaul E-band communication systems.
ESSCIRC
Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani
2012 J jnl
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Bevilacqua, Pietro Andreani
2012 J jnl
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap.
Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
2012 — conf
Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications.
ICICDT
Andrea Neviani, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig
2012 J jnl
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bevilacqua, Pietro Andreani
2011 — conf
A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2.
NORCHIP
Andrea Bevilacqua, Pietro Andreani
2011 J jnl
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS.
IEEE J. Solid State Circuits
Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani
2011 C conf
Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints.
ISCAS
Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
2011 C conf
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory.
ISCAS
Andrea Bevilacqua, Pietro Andreani
2010 J jnl
A 0.06 mm
IEEE J. Solid State Circuits
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
2010 — conf
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS.
ESSCIRC
Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
2010 — conf
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request.
ESSCIRC
Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani
2010 C conf
A digitally programmable ring oscillator in the UWB range.
ISCAS
Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani
2010 C conf
A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks.
ISCAS
Stefano Dal Toso, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
2010 C conf
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end.
ISCAS
Matteo Camponeschi, Andrea Bevilacqua, Andrea Neviani, Pietro Andreani
2010 C conf
Low-power UWB transmitter using a combined mixer and power amplifier.
ISCAS
Silvia Soldà, Michele Caruso, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
2009 — conf
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS.
ESSCIRC
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
2009 J jnl
An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani
2009 J jnl
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems.
IEEE J. Solid State Circuits
Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani
2008 J jnl
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS.
IEEE J. Solid State Circuits
Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2008 C conf
An energy-detector for non-coherent impulse-radio UWB receivers.
ISCAS
Andrea Gerosa, Maurizio Dalla Costa, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani
2008 C conf
Analog decoding of trellis coded modulation for multi-level flash memories.
ISCAS
Silvia Soldà, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
2008 C conf
Design of broadband inductorless LNAs in ultra-scaled CMOS technologies.
ISCAS
Andrea Bevilacqua, Matteo Camponeschi, Marc Tiebout, Andrea Gerosa, Andrea Neviani
2008 — conf
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking.
ISSCC
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani
2008 J jnl
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking.
IEEE J. Solid State Circuits
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani
2007 — conf
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers.
ISSCC
Andrea Bevilacqua, Alessio Vallese, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani
2007 J jnl
An Integrated Solution for Suppressing WLAN Signals in UWB Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani
2007 — conf
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS.
ESSCIRC
Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani
2007 C conf
Quadrature VCOs Based on Coupled PLLs.
ISCAS
Andrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani
2007 J jnl
Transformer-Based Dual-Mode Voltage-Controlled Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bevilacqua, Federico P. Pavan, Christoph Sandner, Andrea Gerosa, Andrea Neviani
2006 — conf
A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection.
ICECS
Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani
2006 — conf
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency.
ICECS
Andrea Maniero, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
2006 J jnl
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Gerosa, Andrea Xotta, Andrea Bevilacqua, Andrea Neviani
2006 C conf
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter.
ISCAS
Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta
2005 J jnl
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bevilacqua, Francesco Svelto
2004 J jnl
An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers.
IEEE J. Solid State Circuits
Andrea Bevilacqua, Ali M. Niknejad
2003 — —
System analysis and circuit design of CMOS integrated wireless receivers for WCDMA and UWB applications.
Andrea Bevilacqua