Anastacia B. Alvarez

33 papers A 1C 10Journal 5Unranked 17

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Performance Analysis of Encoding Schemes in Hyperdimensional Computing for EEG Signals. ICECS Jose Francois Abedejos, Fredrick Angelo R. Galapon, Lawrence Roman A. Quizon, Anastacia B. Alvarez, Adelson Chua
2024	C	`conf`	A Hyperdimensional Computing Architecture with 4.4x Energy Efficiency in 65nm CMOS. ISCAS Fredrick Angelo R. Galapon, Anastacia B. Alvarez
2024	—	`conf`	Federated Learning with MLPerfTiny Tasks and Server-side Momentum. ICMLSC Lawrence Roman A. Quizon, Anastacia B. Alvarez
2023	—	`conf`	Energy-Efficient Sparse Hyperdimensional Computing for Speech Recognition. ISOCC Kim Isaac I. Buelagala, Ginzy S. Javier, Sean Alfred A. Lipardo, James Carlo E. Sorsona, Sherry Joy Alvionne S. Baquiran, Lawrence Roman A. Quizon, Allen Jason Tan, Ryan Albert G. Antonio, Fredrick Angelo R. Galapon, Anastacia B. Alvarez
2023	—	`conf`	Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for TST-MRAM. ISOCC Giussepe Yvanric Galvez, Andrew James Lim, Christopher Jr Camarillo, John Rey Marturillas, Mark Emannuel Teodoro, Ellris Kristian Nuel Urfano, Anastacia B. Alvarez, Ryan Albert G. Antonio, Fredrick Angelo R. Galapon, Sherry Joy Alvionne Baquiran, Allen Jason Tan, Lawrence Roman A. Quizon
2022	C	`conf`	Redundancy Pruning for Binary Hyperdimensional Computing Architectures. ISCAS Ryan Albert G. Antonio, Anastacia B. Alvarez
2021	—	`conf`	A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator. ISOCC Lawrence Roman A. Quizon, Anastacia B. Alvarez, Christoper G. Santos, Marc D. Rosales, John Richard E. Hizon, Maria Patricia Rouelli G. Sabino
2020	—	`conf`	5 Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65 nm CMOS. ISOCC Sean Kane Lloyd M. Quintans, Francesca Bea V. Narcida, Janelle Eira A. Tordesillas, Maria Patricia Rouelli G. Sabino, Anastacia B. Alvarez, Maria Theresa G. de Leon, John Richard E. Hizon, Christopher G. Santos, Marc D. Rosales
2020	—	`conf`	An Energy-Efficient Temperature Sensor Using CMOS Thyristor Delay Elements. ICM Ian Christian Fernandez, Maria Theresa G. de Leon, Anastacia B. Alvarez, Marc D. Rosales
2020	—	`conf`	An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction. ISOCC Christian Joseph Dia, Ralfael Himor, Anastacia B. Alvarez, John Richard E. Hizon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher Santos, Maria Theresa G. de Leon
2020	C	`conf`	Bit-Selection Control for Energy-Efficient Handwritten Digits Recognition Hyperdimensional Computing Architecture. TENCON Ryan Albert G. Antonio, Anastacia B. Alvarez
2020	C	`conf`	Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks. TENCON Michael Joseph Neri, Redentor Immanuel Ridao, Victor Emmanuel Baylosis, Phoebe Meira Chua, Allen Jason Tan, Maria Theresa G. de Leon, John Richard E. Hizon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher Santos, Anastacia B. Alvarez
2020	—	`conf`	Designing a Class E Power Amplifier through Modeling in Verilog-A. ISOCC Arriel Ting, Anastacia B. Alvarez, Maria Theresa G. de Leon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, John Richard E. Hizon, Christopher Santos
2020	J	`jnl`	Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision. IEEE Access Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto
2020	C	`conf`	FPGA-based Features Extraction Sensor for Lettuce Crop. TENCON Maverick Jonas G. Adonis, Renzo S. Forteza, Alaine Richelle C. Ramos, Anastacia B. Alvarez, Maria Theresa G. de Leon, John Richard E. Hizon, Maria Patricia Rouelli Sabino-Santos, Christopher G. Santos, Marc D. Rosales
2019	J	`jnl`	A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process. J. Low Power Electron. Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro
2019	—	`conf`	Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes. ISOCC Phoebe Laine Panis, Maria Sophia Ralota, Joenard Matanguihan, Anastacia B. Alvarez, John Richard E. Hizon, Marc D. Rosales, Christopher Santos, Maria Theresa G. de Leon
2018	C	`conf`	A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications. TENCON Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro
2018	C	`conf`	A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks. TENCON George Procyon Cabrera, Jhelsea Credo, Gio Ishmael Evidente, Ralen Rose Gloria Malatbalat, Steven Lorenzo Mindoro, Arlo Ricardo Sanico, Anastacia B. Alvarez, Chris Vincent J. Densing, Rico Jossel M. Maestro, Marc D. Rosales, Maria Theresa G. de Leon
2018	C	`conf`	A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications. TENCON Uziel Rein Agub, Jhake Zebedee Aquino, Justine Beano, Rommel Monsayac, Anastacia B. Alvarez, Maria Theresa G. de Leon, Chris Vincent J. Densing, John Richard E. Hizon, Rico Jossel M. Maestro, Marc D. Rosales
2018	C	`conf`	A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology. TENCON Zyrel Renzo Sanchez, Sam Jason Vasquez, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Rico Jossel M. Maestro, Maria Theresa G. de Leon, Marc D. Rosales
2018	C	`conf`	An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process. TENCON Gio Ishmael Evidente, Steven Lorenzo Mindoro, Anastacia B. Alvarez, Chris Vincent J. Densing, Rico Jossel M. Maestro, Marc D. Rosales, Maria Theresa G. de Leon
2018	J	`jnl`	Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE J. Solid State Circuits Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto
2018	—	`conf`	Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. NGCAS Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro
2017	—	`conf`	A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. A-SSCC Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto
2017	—	`conf`	EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm A-SSCC Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto
2016	J	`jnl`	Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE J. Solid State Circuits Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto
2015	—	`conf`	14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm. ISSCC Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto
2015	J	`jnl`	A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range. IEEE Trans. Circuits Syst. II Express Briefs Wenfeng Zhao, Anastacia B. Alvarez, Yajun Ha
2013	A	`conf`	Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. ISLPED Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez
2011	—	`conf`	Static Noise Margin of 6T SRAM Cell in 90-nm CMOS. UKSim Christiensen D. C. Arandilla, Anastacia B. Alvarez, Christian Raymund K. Roque
2010	—	`conf`	A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design. UKSim Jestoni V. Zarsuela, Anastacia B. Alvarez, Joy Alinda Reyes
2010	—	`conf`	Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. UKSim Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes