Ananta K. Majhi

27 papers A 7Misc 13Journal 6Unranked 1
YearRankTypeTitle / Venue / Authors
2012 J jnl
NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak
2010 Misc conf
Impact of Temperature on Test Quality.
VLSI Design
Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti
2010 A conf
NIM- a noise index model to estimate delay discrepancies between silicon and simulation.
DATE
Elif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel
2009 Misc conf
Efficient Grouping of Fail Chips for Volume Yield Diagnostics.
VLSI Design
Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi
2008 A conf
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality.
ITC
Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi
2007 Misc conf
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
VTS
Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
2007 Misc conf
Diagnosis of Full Open Defects in Interconnecting Lines.
VTS
Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
2007 A conf
Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects.
ITC
Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke
2007 J jnl
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
CoRR
Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
2007 J jnl
Modeling Power Supply Noise in Delay Testing.
IEEE Des. Test Comput.
Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger
2007 Misc conf
On Performance Testing with Path Delay Patterns.
VTS
Bram Kruseman, Ananta K. Majhi, Guido Gronthoud
2006 A conf
Power Supply Noise in Delay Testing.
ITC
Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger
2005 Misc conf
A New Algorithm for Dynamic Faults Detection in RAMs.
VTS
Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg
2005 A conf
Memory Testing Under Different Stress Conditions: An Industrial Evaluation.
DATE
Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
2005 — conf
Memory testing improvements through different stress conditions.
ESSCIRC
Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
2004 Misc conf
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders.
VTS
Mohamed Azimane, Ananta K. Majhi
2004 A conf
On Hazard-free Patterns for Fine-delay Fault Testing.
ITC
Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger
2004 A conf
Systematic Defects in Deep Sub-Micron Technologies.
ITC
Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede
2003 Misc conf
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.
VTS
Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger
2000 J jnl
Line coverage of path delay faults.
IEEE Trans. Very Large Scale Integr. Syst.
Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik
1998 Misc conf
Automated AC (Timing) Characterization for Digital Circuit Testing.
VLSI Design
S. Balajee, Ananta K. Majhi
1998 Misc conf
Mixed-Signal Test.
VLSI Design
Ananta K. Majhi, Vishwani D. Agrawal
1998 Misc conf
Tutorial: Delay Fault Models and Coverage.
VLSI Design
Ananta K. Majhi, Vishwani D. Agrawal
1996 J jnl
A Novel Path Delay Fault Simulator Using Binary Logic.
VLSI Design
Ananta K. Majhi, James Jacob, Lalit M. Patnaik
1996 Misc conf
On test coverage of path delay faults.
VLSI Design
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
1995 J jnl
A genetic algorithm-based circuit partitioner for MCMs.
Microprocess. Microprogramming
Ananta K. Majhi, Lalit M. Patnaik, Srilata Raman
1995 Misc conf
An efficient automatic test generation system for path delay faults in combinational circuits.
VLSI Design
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal