Ananda Samajdar

31 papers A* 7A 1B 5Journal 13Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads. ISSCC Matthew Cohen, Monodeep Kar, Swagath Venkataramani, Viji Srinivasan, Brian Veraa, Matthew M. Ziegler, Nianzheng Cao, Ashish Ranjan, Joel Silberman, Michael Guillorn, Sandra Woodward, JohnDavid Lancaster, Josh Hursey, Kyu-Hyoun Kim, Alberto Mannari, Amrit Nagarajan, Ananda Samajdar, Bahman Hekmatshoartabari, Bob Galbraith, Ching Zhou, David L. Satterfield, Gregory S. Still, Gustavo Tellez, Indira Nair, Indu Masilamanai, Jinwook Jung, Kavi Randhawa, Marcel Schaal, Martin Lutz, Paul Crumley, Philip Jacob, Prasanth Chatarasi, Radhika Jain, Sae Kyu Lee, Sanchari Sen, Sarada Krithivasan, Scot Rider, Shubham Jain, Siyu Koswatta, Thomas Roewer, Tom Gooding, Victor Ferrari, Vidhi Zalani, Zhibin Ren, Kevin Reick, Lisa Maurice, Christopher J. Gonzalez, Chris Catalino, Ryan Nett, Pong-Fei Lu, Robert M. Senger, Leland Chang
2025	A*	`conf`	CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. HPCA Zishen Wan, Hanchen Yang, Ritik Raj, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	J	`jnl`	CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. CoRR Zishen Wan, Hanchen Yang, Ritik Raj, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	A*	`conf`	NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. DAC Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	J	`jnl`	NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. CoRR Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna
2025	B	`conf`	SCALE-Sim V3: a Modular Cycle-Accurate Systolic Accelerator Simulator for End-To-End System Analysis. ISPASS Ritik Raj, Sarbartha Banerjee, Nikhil Chandra, Zishen Wan, Jianming Tong, Ananda Samajdar, Tushar Krishna
2025	J	`jnl`	SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis. CoRR Ritik Raj, Sarbartha Banerjee, Nikhil Chandra, Zishen Wan, Jianming Tong, Ananda Samajdar, Tushar Krishna
2024	B	`conf`	Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. ISPASS Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Ananda Samajdar, Yingyan Celine Lin, Tushar Krishna, Arijit Raychowdhury
2024	J	`jnl`	Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. CoRR Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan Celine Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, Arijit Raychowdhury
2024	J	`jnl`	Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. IEEE Trans. Circuits Syst. Artif. Intell. Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, Arijit Raychowdhury
2023	A	`conf`	AIrchitect: Automating Hardware Architecture and Mapping Optimization. DATE Ananda Samajdar, Jan Moritz Joseph, Tushar Krishna
2022	—	`—`	Methodology and Analysis for Efficient Custom Architecture Design using Machine Learning. Ananda Samajdar
2022	A*	`conf`	Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. DAC Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna
2021	J	`jnl`	AIRCHITECT: Learning Custom Architecture Design and Mapping Space. CoRR Ananda Samajdar, Jan Moritz Joseph, Matthew Denton, Tushar Krishna
2021	—	`conf`	Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2021	A*	`conf`	RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. DAC Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna
2021	J	`jnl`	RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. CoRR Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna
2021	J	`jnl`	Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration. CoRR Ananda Samajdar, Michael Pellauer, Tushar Krishna
2020	B	`conf`	A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim. ISPASS Ananda Samajdar, Jan Moritz Joseph, Yuhao Zhu, Paul N. Whatmough, Matthew Mattina, Tushar Krishna
2020	J	`jnl`	Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2020	B	`conf`	CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices. ISPASS Parth Mannan, Ananda Samajdar, Tushar Krishna
2020	J	`jnl`	CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices. CoRR Parth Mannan, Ananda Samajdar, Tushar Krishna
2020	—	`book`	Data Orchestration in Deep Learning Accelerators Tushar Krishna, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Ananda Samajdar
2020	A*	`conf`	SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training. HPCA Eric Qin, Ananda Samajdar, Hyoukjun Kwon, Vineet Nadella, Sudarshan Srinivasan, Dipankar Das, Bharat Kaul, Tushar Krishna
2019	B	`conf`	Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. FPL Ananda Samajdar, Tushar Garg, Tushar Krishna, Nachiket Kapre
2018	J	`jnl`	A Communication-Centric Approach for Designing Flexible DNN Accelerators. IEEE Micro Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna
2018	A*	`conf`	GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware. MICRO Ananda Samajdar, Parth Mannan, Kartikay Garg, Tushar Krishna
2018	J	`jnl`	GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware. CoRR Ananda Samajdar, Parth Mannan, Kartikay Garg, Tushar Krishna
2018	A*	`conf`	MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects. ASPLOS Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna
2018	J	`jnl`	SCALE-Sim: Systolic CNN Accelerator. CoRR Ananda Samajdar, Yuhao Zhu, Paul N. Whatmough, Matthew Mattina, Tushar Krishna
2017	—	`conf`	Rethinking NoCs for Spatial Neural Network Accelerators. NOCS Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna