Anand Rajaram

20 papers A* 3A 3Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
GOALPlace: Begin with the End in Mind.
ISPD
Anthony Agnesina, Rongjian Liang, Geraldo Pradipta, Anand Rajaram, Haoxing Ren
2024 A* conf
DGR: Differentiable Global Router.
DAC
Wei Li, Rongjian Liang, Anthony Agnesina, Haoyu Yang, Chia-Tung Ho, Anand Rajaram, Haoxing Ren
2024 J jnl
GOALPlace: Begin with the End in Mind.
CoRR
Anthony Agnesina, Rongjian Liang, Geraldo Pradipta, Anand Rajaram, Haoxing Ren
2023 — conf
BufFormer: A Generative ML Framework for Scalable Buffering.
ASP-DAC
Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren
2011 J jnl
Robust Chip-Level Clock Tree Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Rajaram, David Z. Pan
2010 J jnl
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Rajaram, David Z. Pan
2009 A conf
Analysis and optimization of NBTI induced clock skew in gated clock trees.
DATE
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan
2008 — conf
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.
ASP-DAC
Anand Rajaram, David Z. Pan
2008 — conf
Practical Clock Tree Robustness Signoff Metrics.
ISQED
Anand Rajaram, Raguram Damodaran, Arjun Rajagopal
2008 A* conf
Robust chip-level clock tree synthesis for SOC designs.
DAC
Anand Rajaram, David Z. Pan
2007 — conf
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure.
ISSCC
Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan
2007 — conf
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.
ISQED
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
2006 J jnl
Analytical bound for unwanted clock skew due to wire width variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo
2006 — conf
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction.
ISQED
Anand Rajaram, David Z. Pan
2006 J jnl
Reducing clock skew variability via crosslinks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
2006 — conf
Variation tolerant buffered clock network synthesis with cross links.
ISPD
Anand Rajaram, David Z. Pan
2005 — conf
Improved algorithms for link-based non-tree clock networks for skew variability reduction.
ISPD
Anand Rajaram, David Z. Pan, Jiang Hu
2005 A conf
Practical techniques to reduce skew and its variations in buffered clock networks.
ICCAD
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
2004 A* conf
Reducing clock skew variability via cross links.
DAC
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
2003 A conf
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.
ICCAD
Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu