Anand Raghunathan

392 papers A* 54A 80B 7C 11Misc 36Journal 162Unranked 38
YearRankTypeTitle / Venue / Authors
2026 J jnl
Characterizing VLA Models: Identifying the Action Generation Bottleneck for Edge AI Architectures.
CoRR
Manoj Vishwanathan, Suvinay Subramanian, Anand Raghunathan
2026 J jnl
Learning to Localize Leakage of Cryptographic Sensitive Variables.
Trans. Mach. Learn. Res.
Jimmy Gammell, Anand Raghunathan, Abolfazl Hashemi, Kaushik Roy
2026 J jnl
Softprox: A Post-Finetuning Methodology to Mitigate Softmax Bottlenecks in Transformer Workloads.
IEEE Trans. Circuits Syst. Artif. Intell.
Aradhana Mohan Parvathy, Sourjya Roy, Soumendu Kumar Ghosh, Arnab Raha, Deepak Mathaikutty, Anand Raghunathan
2025 A* conf
3D-CIMlet: A Chiplet Co-Design Framework for Heterogeneous In-Memory Acceleration of Edge LLM Inference and Continual Learning.
DAC
Shuting Du, Luqi Zheng, Aradhana Mohan Parvathy, Feifan Xie, Tiwei Wei, Anand Raghunathan, Haitong Li
2025 J jnl
BCQ: Block Clustered Quantization for 4-bit (W4A4) LLM Inference.
CoRR
Reena Elangovan, Charbel Sakr, Anand Raghunathan, Brucek Khailany
2025 J jnl
Experts are all you need: A Composable Framework for Large Language Model Inference.
CoRR
Shrihari Sridharan, Sourjya Roy, Anand Raghunathan, Kaushik Roy
2025 J jnl
GradientSpace: Unsupervised Data Clustering for Improved Instruction Tuning.
CoRR
Shrihari Sridharan, Deepak Ravikumar, Anand Raghunathan, Kaushik Roy
2025 J jnl
KV-CAR: KV Cache Compression using Autoencoders and KV Reuse in Large Language Models.
CoRR
Sourjya Roy, Shrihari Sridharan, Surya Selvam, Anand Raghunathan
2025 J jnl
LO-BCQ: Locally Optimal Block Clustered Quantization for 4-bit (W4A4) LLM Inference.
Trans. Mach. Learn. Res.
Reena Elangovan, Charbel Sakr, Anand Raghunathan, Brucek Khailany
2025 J jnl
Learning to Localize Leakage of Cryptographic Sensitive Variables.
CoRR
Jimmy Gammell, Anand Raghunathan, Abolfazl Hashemi, Kaushik Roy
2025 — conf
ML-Enhanced Performance and Power Estimation for DNNs on Heterogenous SoCs.
MLCAD
Surya Selvam, Jacob R. Stevens, Sujit Dey, Anand Raghunathan
2025 A conf
ML-Power: Machine Learning based Power Estimation for SoCs.
ISLPED
Sujay Pandit, Sujit Dey, Anand Raghunathan
2025 — conf
SimCache: Similarity Caching for Efficient VLM-based Scene Understanding.
CVPR Workshops
Surya Selvam, Ravi K. Rajendran, Murugan Sankaradas, Anand Raghunathan, Srimat T. Chakradhar
2024 J jnl
Efficient Batched Inference in Conditional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Surya Selvam, Amrit Nagarajan, Anand Raghunathan
2024 A* conf
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms.
DAC
Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan
2024 J jnl
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms.
CoRR
Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan
2024 — conf
Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks.
ECML/PKDD (5)
Amrit Nagarajan, Anand Raghunathan
2024 J jnl
LRMP: Layer Replication with Mixed Precision for spatial in-memory DNN accelerators.
Frontiers Artif. Intell.
Abinand Nallathambi, Christin David Bose, Wilfried Haensch, Anand Raghunathan
2024 J jnl
MixTrain: accelerating DNN training via input mixing.
Frontiers Artif. Intell.
Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan
2024 J jnl
PArtNNer: Platform-Agnostic Adaptive Edge-Cloud DNN Partitioning for Minimizing End-to-End Latency.
ACM Trans. Embed. Comput. Syst.
Soumendu Kumar Ghosh, Arnab Raha, Vijay Raghunathan, Anand Raghunathan
2024 J jnl
Power side-channel leakage localization through adversarial training of deep neural networks.
CoRR
Jimmy Gammell, Anand Raghunathan, Kaushik Roy
2024 J jnl
SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks.
CoRR
Niharika Thakuria, Akul Malhotra, Sandeep Krishna Thirumala, Reena Elangovan, Anand Raghunathan, Sumeet Kumar Gupta
2023 J jnl
Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators.
CoRR
Sourjya Roy, Cheng Wang, Anand Raghunathan
2023 — conf
EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems.
SOCC
Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey
2023 J jnl
FASTRAIN-GNN: Fast and Accurate Self-Training for Graph Neural Networks.
Trans. Mach. Learn. Res.
Amrit Nagarajan, Anand Raghunathan
2023 J jnl
Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks.
CoRR
Amrit Nagarajan, Anand Raghunathan
2023 J jnl
LRMP: Layer Replication with Mixed Precision for Spatial In-memory DNN Accelerators.
CoRR
Abinand Nallathambi, Christin David Bose, Wilfried Haensch, Anand Raghunathan
2023 — conf
TokenDrop + BucketSampler: Towards Efficient Padding-free Fine-tuning of Language Models.
EMNLP (Findings)
Amrit Nagarajan, Anand Raghunathan
2023 J jnl
X-Former: In-Memory Acceleration of Transformers.
CoRR
Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan
2023 J jnl
X-Former: In-Memory Acceleration of Transformers.
IEEE Trans. Very Large Scale Integr. Syst.
Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan
2022 J jnl
A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks.
CoRR
Wilfried Haensch, Anand Raghunathan, Kaushik Roy, Bhaswar Chakrabarti, Charudatta M. Phatak, Cheng Wang, Supratik Guha
2022 A* conf
A cross-layer approach to cognitive computing: invited.
DAC
Gobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy
2022 A conf
Approximate Computing and the Efficient Machine Learning Expedition.
ICCAD
Jörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis
2022 J jnl
Approximate Computing and the Efficient Machine Learning Expedition.
CoRR
Jörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis
2022 — ch.
Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective.
Approximate Computing
Sourav Sanyal, Shubham Negi, Anand Raghunathan, Kaushik Roy
2022 J jnl
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration.
ACM Trans. Design Autom. Electr. Syst.
Reena Elangovan, Shubham Jain, Anand Raghunathan
2022 B conf
AxFormer: Accuracy-driven Approximation of Transformers for Faster, Smaller and more Accurate NLP Models.
IJCNN
Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan
2022 J jnl
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads.
IEEE Trans. Very Large Scale Integr. Syst.
Mustafa Fayez Ali, Sourjya Roy, Utkarsh Saxena, Tanvi Sharma, Anand Raghunathan, Kaushik Roy
2022 J jnl
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey
2022 A* conf
Efficiency attacks on spiking neural networks.
DAC
Sarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy, Anand Raghunathan
2022 A* conf
Efficient ensembles of graph neural networks.
DAC
Amrit Nagarajan, Jacob R. Stevens, Anand Raghunathan
2022 A conf
Energy Efficient Cache Design with Piezoelectric FETs.
ISLPED
Reena Elangovan, Ashish Ranjan, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan
2022 A conf
Layerwise Disaggregated Evaluation of Spiking Neural Networks.
ISLPED
Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan
2022 J jnl
STeP-CiM: Strain-enabled Ternary Precision Computation-in-Memory based on Non-Volatile 2D Piezoelectric Transistors.
CoRR
Niharika Thakuria, Reena Elangovan, Sandeep Krishna Thirumala, Anand Raghunathan, Sumeet Kumar Gupta
2022 A conf
Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural Networks.
ICCAD
Aradhana Mohan Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan
2021 — conf
Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems.
AICAS
Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey
2021 — conf
Design Tools for Resistive Crossbar based Machine Learning Accelerators.
AICAS
Indranil Chakraborty, Sourjya Roy, Shrihari Sridharan, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Anand Raghunathan
2021 A conf
Efficacy of Pruning in Ultra-Low Precision DNNs.
ISLPED
Sanchari Sen, Swagath Venkataramani, Anand Raghunathan
2021 A* conf
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks.
DAC
Jacob R. Stevens, Dipankar Das, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan
2021 J jnl
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks.
CoRR
Jacob R. Stevens, Dipankar Das, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan
2021 J jnl
HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices.
CoRR
Malin Prematilake, Younghyun Kim, Vijay Raghunathan, Anand Raghunathan, Niraj K. Jha
2021 J jnl
PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan
2021 J jnl
PIM-DRAM: Accelerating Machine Learning Workloads using Processing in Commodity DRAM.
CoRR
Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan
2021 J jnl
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan
2021 A* conf
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers.
DAC
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
2021 J jnl
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers.
CoRR
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
2021 J jnl
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan
2021 A conf
Value Similarity Extensions for Approximate Computing in General-Purpose Processors.
DATE
Younghoon Kim, Swagath Venkataramani, Sanchari Sen, Anand Raghunathan
2020 — conf
A Case for Generalizable DNN Cost Models for Mobile Devices.
IISWC
Vinod Ganesan, Surya Selvam, Sanchari Sen, Pratyush Kumar, Anand Raghunathan
2020 J jnl
Adversarial Sparsity Attacks on Deep Neural Networks.
CoRR
Sarada Krithivasan, Sanchari Sen, Anand Raghunathan
2020 J jnl
Approximate Memory Compression.
IEEE Trans. Very Large Scale Integr. Syst.
Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan
2020 J jnl
Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration.
CoRR
Reena Elangovan, Shubham Jain, Anand Raghunathan
2020 A conf
Communication-efficient View-Pooling for Distributed Multi-View Neural Networks.
DATE
Manik Singhal, Vijay Raghunathan, Anand Raghunathan
2020 J jnl
CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems.
ACM Trans. Embed. Comput. Syst.
Shubham Jain, Anand Raghunathan
2020 J jnl
DyVEDeep: Dynamic Variable Effort Deep Neural Networks.
ACM Trans. Embed. Comput. Syst.
Sanjay Ganapathy, Swagath Venkataramani, Giridhur Sriraman, Balaraman Ravindran, Anand Raghunathan
2020 A* conf
EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness Against Adversarial Attacks.
ICLR
Sanchari Sen, Balaraman Ravindran, Anand Raghunathan
2020 J jnl
EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness against Adversarial Attacks.
CoRR
Sanchari Sen, Balaraman Ravindran, Anand Raghunathan
2020 A conf
Emerging Neural Workloads and Their Impact on Hardware.
DATE
David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, Xiaobo Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael T. Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin
2020 J jnl
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks.
IEEE Access
Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy
2020 J jnl
Gradual Channel Pruning while Training using Feature Relevance Scores for Convolutional Neural Networks.
CoRR
Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy
2020 J jnl
Logic Synthesis of Approximate Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Swagath Venkataramani, Vivek Joy Kozhikkottu, Amit Sabne, Kaushik Roy, Anand Raghunathan
2020 J jnl
Optimizing Transformers with Approximate Computing for Faster, Smaller and more Accurate NLP Models.
CoRR
Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan
2020 B conf
Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks.
IJCNN
Sourjya Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, Anand Raghunathan
2020 J jnl
Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks.
CoRR
Sourjya Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, Anand Raghunathan
2020 J jnl
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges.
Proc. IEEE
Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Sourjya Roy, Shrihari Sridharan, Amogh Agrawal, Anand Raghunathan, Kaushik Roy
2020 J jnl
Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarada Krithivasan, Sanchari Sen, Anand Raghunathan
2020 A conf
Sparsity-Aware Caches to Accelerate Deep Neural Networks.
DATE
Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan
2020 A conf
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks.
DATE
Sandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan
2020 J jnl
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan
2020 J jnl
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems.
CoRR
Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan
2019 — ch.
Automatic Synthesis Techniques for Approximate Circuits.
Approximate Circuits
Ashish Ranjan, Swagath Venkataramani, Shubham Jain, Younghoon Kim, Shankar Ganesh Ramasubramanian, Arnab Raha, Kaushik Roy, Anand Raghunathan
2019 A conf
Data Subsetting: A Data-Centric Approach to Approximate Computing.
DATE
Younghoon Kim, Swagath Venkataramani, Nitin Chandrachoodan, Anand Raghunathan
2019 A conf
Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks.
ISLPED
Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan
2019 A* conf
Manna: An Accelerator for Memory-Augmented Neural Networks.
MICRO
Jacob R. Stevens, Ashish Ranjan, Dipankar Das, Bharat Kaul, Anand Raghunathan
2019 J jnl
Neural network accelerator design with resistive crossbars: Opportunities and challenges.
IBM J. Res. Dev.
Shubham Jain, Aayush Ankit, Indranil Chakraborty, Tayfun Gokmen, Malte J. Rasch, Wilfried Haensch, Kaushik Roy, Anand Raghunathan
2019 A conf
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation.
ISLPED
Sandeep Krishna Thirumala, Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
2019 — conf
Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing.
COMAD/CODS
Athindran Ramesh Kumar, Balaraman Ravindran, Anand Raghunathan
2019 J jnl
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks.
IEEE Trans. Computers
Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan
2019 J jnl
TiM-DNN: Ternary in-Memory accelerator for Deep Neural Networks.
CoRR
Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan
2019 J jnl
Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support.
CoRR
Sandeep Krishna Thirumala, Yi-Tse Hung, Shubham Jain, Arnab Raha, Niharika Thakuria, Vijay Raghunathan, Anand Raghunathan, Zhihong Chen, Sumeet Kumar Gupta
2019 A* conf
X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks.
DAC
Ashish Ranjan, Shubham Jain, Jacob R. Stevens, Dipankar Das, Bharat Kaul, Anand Raghunathan
2018 J jnl
A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensory Data Transfer.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Setareh Behroozi, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim
2018 A conf
ACCLIB: Accelerators as libraries.
DATE
Jacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan
2018 J jnl
Approximate Computing for Long Short Term Memory (LSTM) Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sanchari Sen, Anand Raghunathan
2018 A conf
AxBA: an approximate bus architecture framework.
ICCAD
Jacob R. Stevens, Ashish Ranjan, Anand Raghunathan
2018 J jnl
Computing in Memory With Spin-Transfer Torque Magnetic RAM.
IEEE Trans. Very Large Scale Integr. Syst.
Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
2018 A conf
Computing-in-memory with spintronics.
DATE
Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan
2018 J jnl
Energy Efficient Neural Computing: A Study of Cross-Layer Approximations.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Bing Han, Parami Wijesinghe, Akhilesh Jaiswal, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy
2018 J jnl
Energy-Efficient Neural Computing with Approximate Multipliers.
ACM J. Emerg. Technol. Comput. Syst.
Syed Shakib Sarwar, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, Kaushik Roy
2018 J jnl
Guest Editors' Introduction.
IEEE Embed. Syst. Lett.
Sybille Hellebrand, Jörg Henkel, Anand Raghunathan, Hans-Joachim Wunderlich
2018 J jnl
Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing.
CoRR
Athindran Ramesh Kumar, Balaraman Ravindran, Anand Raghunathan
2018 J jnl
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars.
CoRR
Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan
2018 C conf
SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones.
ICCD
Kyuin Lee, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim
2017 A* conf
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
DAC
Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
2017 A conf
A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks.
ISLPED
Arnab Roy, Swagath Venkataramani, Neel Gala, Sanchari Sen, Kamakoti Veezhinathan, Anand Raghunathan
2017 A conf
AXSERBUS: A quality-configurable approximate serial bus for energy-efficient sensing.
ISLPED
Younghyun Kim, Setareh Behroozi, Vijay Raghunathan, Anand Raghunathan
2017 J jnl
Approximate Error Detection With Stochastic Checkers.
IEEE Trans. Very Large Scale Integr. Syst.
Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti
2017 A conf
Approximate computing for spiking neural networks.
DATE
Sanchari Sen, Swagath Venkataramani, Anand Raghunathan
2017 A conf
Approximate memory compression for energy-efficiency.
ISLPED
Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan
2017 J jnl
CABA: Continuous Authentication Based on BioAura.
IEEE Trans. Computers
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2017 J jnl
Computing in Memory with Spin-Transfer Torque Magnetic RAM.
CoRR
Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
2017 J jnl
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.
IEEE Trans. Multi Scale Comput. Syst.
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2017 J jnl
Design and Management of Battery-Supercapacitor Hybrid Electrical Energy Storage Systems for Regulation Services.
IEEE Trans. Multi Scale Comput. Syst.
Younghyun Kim, Vijay Raghunathan, Anand Raghunathan
2017 J jnl
DyVEDeep: Dynamic Variable Effort Deep Neural Networks.
CoRR
Sanjay Ganapathy, Swagath Venkataramani, Balaraman Ravindran, Anand Raghunathan
2017 J jnl
Energy-Efficient Object Detection Using Semantic Decomposition.
IEEE Trans. Very Large Scale Integr. Syst.
Priyadarshini Panda, Swagath Venkataramani, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy
2017 J jnl
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations.
IEEE Trans. Very Large Scale Integr. Syst.
Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan
2017 B conf
Model-based Iterative CT Image Reconstruction on GPUs.
PPoPP
Amit Sabne, Xiao Wang, Sherman J. Kisner, Charles A. Bouman, Anand Raghunathan, Samuel P. Midkiff
2017 A conf
STAxCache: An approximate, energy efficient STT-MRAM cache.
DATE
Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
2017 A* conf
ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks.
ISCA
Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan
2017 J jnl
SparCE: Sparsity aware General Purpose Core Extensions to Accelerate Deep Neural Networks.
CoRR
Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan
2017 J jnl
Wearable Medical Sensor-Based System Design: A Survey.
IEEE Trans. Multi Scale Comput. Syst.
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2016 Misc conf
Approximate Computing.
VLSID
Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2016 A conf
Approximation through logic isolation for the design of quality configurable circuits.
DATE
Shubham Jain, Swagath Venkataramani, Anand Raghunathan
2016 J jnl
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes.
ACM J. Emerg. Technol. Comput. Syst.
A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2016 J jnl
Cache Design with Domain Wall Memory.
IEEE Trans. Computers
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2016 A* conf
Designing approximate circuits using clock overgating.
DAC
Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2016 J jnl
EMBIRA: An Accelerator for Model-Based Iterative Reconstruction.
IEEE Trans. Very Large Scale Integr. Syst.
Junshi Liu, Swagath Venkataramani, Singanallur V. Venkatakrishnan, Yun Pan, Charles A. Bouman, Anand Raghunathan
2016 — conf
Efficient embedded learning for IoT devices.
ASP-DAC
Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2016 J jnl
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches.
IEEE Trans. Very Large Scale Integr. Syst.
Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy
2016 J jnl
Emulation-Based Analysis of System-on-Chip Performance Under Variations.
IEEE Trans. Very Large Scale Integr. Syst.
Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey
2016 B conf
High performance model based image reconstruction.
PPoPP
Xiao Wang, Amit Sabne, Sherman J. Kisner, Anand Raghunathan, Charles A. Bouman, Samuel P. Midkiff
2016 J jnl
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.
IEEE Des. Test
Kaushik Roy, Byunghoo Jung, Dimitrios Peroulis, Anand Raghunathan
2016 A* conf
Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems.
DAC
Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2016 J jnl
Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing.
CoRR
Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2016 A conf
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing.
DATE
Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2016 Misc conf
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices.
VLSID
Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy
2016 J jnl
Physiological Information Leakage: A New Frontier in Health Information Security.
IEEE Trans. Emerg. Top. Comput.
Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2016 A conf
STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection.
ISLPED
Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti
2016 J jnl
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy
2016 J jnl
Spin-Transfer Torque Memories: Devices, Circuits, and Systems.
Proc. IEEE
Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy
2016 J jnl
Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC.
ACM J. Emerg. Technol. Comput. Syst.
Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2015 J jnl
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding.
ACM Trans. Design Autom. Electr. Syst.
Ali Mirtar, Sujit Dey, Anand Raghunathan
2015 — conf
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications.
ISVLSI
Kaushik Roy, Anand Raghunathan
2015 A* conf
Approximate computing and the quest for computing efficiency.
DAC
Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2015 A* conf
Approximate storage for energy efficient spintronic memories.
DAC
Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
2015 A conf
Asymmetric underlapped FinFET based robust SRAM design at 7nm node.
DATE
A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2015 A conf
Computing approximately, and efficiently.
DATE
Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2015 A conf
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s.
DATE
Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan
2015 J jnl
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage.
ACM J. Emerg. Technol. Comput. Syst.
Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2015 J jnl
Energy-Efficient Long-term Continuous Personal Health Monitoring.
IEEE Trans. Multi Scale Comput. Syst.
Arsalan Mohsen Nia, Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015 J jnl
Exploring Spin-Transfer-Torque Devices for Logic Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy
2015 J jnl
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management.
IEEE Trans. Very Large Scale Integr. Syst.
Ali Mirtar, Sujit Dey, Anand Raghunathan
2015 J jnl
Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing.
CoRR
Priyadarshini Panda, Abhronil Sengupta, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2015 A conf
Quality configurable reduce-and-rank for energy efficient approximate computing.
DATE
Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan
2015 A* conf
Scalable-effort classifiers for energy-efficient machine learning.
DAC
Swagath Venkataramani, Anand Raghunathan, Jie Liu, Mohammed Shoaib
2015 A conf
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing.
DATE
Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
2015 J jnl
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.
IEEE J. Biomed. Health Informatics
Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
2015 A* conf
Vibration-based secure side channel for medical devices.
DAC
Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan
2015 J jnl
Yield, Area and Energy Optimization in Stt-MRAMs using failure aware ECC.
CoRR
Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2014 Misc ed.
2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014
CASES
Karam S. Chatha, Rolf Ernst, Anand Raghunathan, Ravishankar R. Iyer
2014 J jnl
A defense framework against malware and vulnerability exploits.
Int. J. Inf. Sec.
Meng Zhang, Anand Raghunathan, Niraj K. Jha
2014 A conf
ASLAN: Synthesis of approximate sequential circuits.
DATE
Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014 — conf
Approximate computing for efficient information processing.
ESTIMedia
Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2014 A conf
AxNN: energy-efficient neuromorphic systems using approximate computing.
ISLPED
Swagath Venkataramani, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
2014 — conf
Design and management of hybrid electrical energy storage systems for regulation services.
IGCC
Younghyun Kim, Vijay Raghunathan, Anand Raghunathan
2014 A conf
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing.
ISLPED
Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2014 A* conf
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies.
ISCA
Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014 J jnl
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.
CoRR
Deliang Fan, Yong Shim, Anand Raghunathan, Kaushik Roy
2014 J jnl
Scalable Effort Hardware Design.
IEEE Trans. Very Large Scale Integr. Syst.
Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
2014 — conf
ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters.
USENIX ATC
Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar
2014 A conf
StoRM: a stochastic recognition and mining processor.
ISLPED
Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014 J jnl
Trustworthiness of Medical Devices and Body Area Networks.
Proc. IEEE
Meng Zhang, Anand Raghunathan, Niraj K. Jha
2014 A* conf
Variation Aware Cache Partitioning for Multithreaded Programs.
DAC
Vivek Joy Kozhikkottu, Abhisek Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan
2014 A conf
Variation tolerant design of a vector processor for recognition, mining and synthesis.
ISLPED
Vivek Joy Kozhikkottu, Swagath Venkataramani, Sujit Dey, Anand Raghunathan
2013 A* conf
Analysis and characterization of inherent application resilience for approximate computing.
DAC
Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013 Misc conf
Approximate computing: An integrated hardware approach.
ACSSC
Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013 C conf
Approximate computing: Energy-efficient computing with good-enough results.
IOLTS
Anand Raghunathan, Kaushik Roy
2013 A conf
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes.
DATE
Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2013 Misc conf
Emerging Frontiers in Embedded Security.
VLSI Design
Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha
2013 Misc conf
Energy-efficient and Secure Sensor Data Transmission Using Encompression.
VLSI Design
Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha
2013 — conf
Energy-efficient recognition and mining processor using scalable effort design.
CICC
Vinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan
2013 J jnl
Improving the Trustworthiness of Medical Device Software with Formal Verification Methods.
IEEE Embed. Syst. Lett.
Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2013 Misc conf
Localized Heating for Building Energy Efficiency.
VLSI Design
Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan
2013 J jnl
Low-Power Digital Signal Processing Using Approximate Adders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy
2013 J jnl
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling.
ACM Trans. Embed. Comput. Syst.
Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
2013 J jnl
MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection.
IEEE Trans. Biomed. Circuits Syst.
Meng Zhang, Anand Raghunathan, Niraj K. Jha
2013 A conf
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches.
ISLPED
Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2013 A* conf
Quality programmable vector processors for approximate computing.
MICRO
Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013 — conf
Reading spin-torque memory with spin-torque sensors.
NANOARCH
Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2013 A* conf
Relax-and-retime: a methodology for energy-efficient recovery based design.
DAC
Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Adithya Parandhaman, Anand Raghunathan
2013 A conf
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits.
DATE
Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2013 A* conf
Towards trustworthy medical devices and body area networks.
DAC
Meng Zhang, Anand Raghunathan, Niraj K. Jha
2012 J jnl
A Trusted Virtual Machine in an Untrusted Management Environment.
IEEE Trans. Serv. Comput.
Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2012 — conf
Adaptation of video encoding to address dynamic thermal management effects.
IGCC
Ali Mirtar, Sujit Dey, Anand Raghunathan
2012 A conf
Automatic generation of software pipelines for heterogeneous parallel systems.
SC
Jacques A. Pienaar, Srimat T. Chakradhar, Anand Raghunathan
2012 J jnl
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations.
IEEE Trans. Very Large Scale Integr. Syst.
W. Paul Griffin, Anand Raghunathan, Kaushik Roy
2012 B conf
Functional analysis of circuits under timing variations.
ETS
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
2012 A* conf
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
DAC
Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy
2012 J jnl
Guest Editors' Introduction: Green Buildings.
IEEE Des. Test Comput.
Yuvraj Agarwal, Anand Raghunathan
2012 J jnl
INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment.
ACM Trans. Embed. Comput. Syst.
Divya Arora, Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2012 C conf
On Modeling and Evaluation of Logic Circuits under Timing Variations.
DSD
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
2012 C conf
PIC: Partitioned Iterative Convergence for Clusters.
CLUSTER
Reza Farivar, Anand Raghunathan, Srimat T. Chakradhar, Harshit Kharbanda, Roy H. Campbell
2012 A* conf
Recovery-based design for variation-tolerant SoCs.
DAC
Vivek Joy Kozhikkottu, Sujit Dey, Anand Raghunathan
2012 A* conf
SALSA: systematic logic synthesis of approximate circuits.
DAC
Swagath Venkataramani, Amit Sabne, Vivek Joy Kozhikkottu, Kaushik Roy, Anand Raghunathan
2012 J jnl
Secure reconfiguration of software-defined radio.
ACM Trans. Embed. Comput. Syst.
Chunxiao Li, Niraj K. Jha, Anand Raghunathan
2012 A conf
TapeCache: a high density, energy efficient cache based on domain wall memory.
ISLPED
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2012 A* conf
Tarazu: optimizing MapReduce on heterogeneous clusters.
ASPLOS
Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar
2012 J jnl
Variation-Aware Voltage Level Selection.
IEEE Trans. Very Large Scale Integr. Syst.
Saumya Chandra, Anand Raghunathan, Sujit Dey
2011 J jnl
A framework for defending embedded systems against software attacks.
ACM Trans. Embed. Comput. Syst.
Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2011 A conf
Design of voltage-scalable meta-functions for approximate computing.
DATE
Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy
2011 A* conf
Dynamic effort scaling: managing the quality-efficiency tradeoff.
DAC
Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar
2011 — conf
Energy efficient many-core processor for recognition and mining using spin-based memory.
NANOARCH
Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
2011 A conf
IMPACT: imprecise adders for low-power approximate computing.
ISLPED
Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy
2011 A conf
MACACO: Modeling and analysis of circuits for approximate computing.
ICCAD
Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan
2011 A conf
MDR: performance model driven runtime for heterogeneous parallel platforms.
ICS
Jacques A. Pienaar, Anand Raghunathan, Srimat T. Chakradhar
2011 A conf
VESPA: Variability emulation for System-on-Chip performance analysis.
DATE
Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey
2010 C conf
A Secure User Interface for Web Applications Running Under an Untrusted Operating System.
CIT
Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2010 A* conf
Best-effort computing: re-thinking parallel software and hardware.
DAC
Srimat T. Chakradhar, Anand Raghunathan
2010 — conf
Best-effort semantic document search on GPUs.
GPGPU
Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi
2010 A conf
Exploiting the forgiving nature of applications for scalable parallel execution.
IPDPS
Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Surendra Byna
2010 Misc conf
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.
VLSI Design
Kaushik Roy, Byunghoo Jung, Anand Raghunathan
2010 A* conf
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
DAC
Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar
2010 — conf
Secure Virtual Machine Execution under an Untrusted Management OS.
IEEE CLOUD
Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2010 Misc conf
Special session 11B: Hot topic hardware security: Design, test and verification issues.
VTS
Swarup Bhunia, Anand Raghunathan
2010 J jnl
Variation-Aware System-Level Power Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2009 A conf
A framework for efficient and scalable execution of domain-specific templates on GPUs.
IPDPS
Narayanan Sundaram, Anand Raghunathan, Srimat T. Chakradhar
2009 A conf
An architecture for secure software defined radio.
DATE
Chunxiao Li, Anand Raghunathan, Niraj K. Jha
2009 A conf
Best-effort parallel execution framework for Recognition and mining applications.
IPDPS
Jiayuan Meng, Srimat T. Chakradhar, Anand Raghunathan
2009 Misc conf
Coping with Variations through System-Level Design.
VLSI Design
Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy
2009 J jnl
Variation-Tolerant Dynamic Power Management at the System-Level.
IEEE Trans. Very Large Scale Integr. Syst.
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2008 J jnl
Analysis and design of a hardware/software trusted platform module for embedded systems.
ACM Trans. Embed. Comput. Syst.
Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2008 B conf
Dynamic Binary Instrumentation-Based Framework for Malware Defense.
DIMVA
Najwa Aaraj, Anand Raghunathan, Niraj K. Jha
2008 J jnl
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst.
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2008 A conf
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor.
DATE
Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar
2008 J jnl
Systematic Software-Based Self-Test for Pipelined Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
2007 J jnl
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007 A* conf
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.
DAC
Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan
2007 J jnl
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2007 J jnl
Architectural Support for Run-Time Validation of Program Data Properties.
IEEE Trans. Very Large Scale Integr. Syst.
Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007 J jnl
Automated Energy/Performance Macromodeling of Embedded Software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007 Misc conf
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.
VLSI Design
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan
2007 J jnl
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.
IEEE Trans. Very Large Scale Integr. Syst.
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2007 A conf
Energy and execution time analysis of a software-based trusted platform module.
DATE
Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007 J jnl
Energy-optimizing source code transformations for operating system-driven embedded software.
ACM Trans. Embed. Comput. Syst.
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007 J jnl
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. Very Large Scale Integr. Syst.
Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2007 J jnl
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007 J jnl
Guest Editors' Introduction: Security and Trust in Embedded-Systems Design.
IEEE Des. Test Comput.
Patrick Schaumont, Anand Raghunathan
2007 J jnl
Hardware Accelerated Power Estimation
CoRR
Joel Coburn, Srivaths Ravi, Anand Raghunathan
2007 J jnl
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007 J jnl
Hybrid Simulation for Energy Estimation of Embedded Software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007 A ed.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007
ISLPED
Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan
2007 A* conf
System-on-Chip Power Management Considering Leakage Power Variations.
DAC
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2006 J jnl
A Scalable Synthesis Methodology for Application-Specific Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 J jnl
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.
IEEE Trans. Mob. Comput.
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 C conf
Active Learning Driven Data Acquisition for Sensor Networks.
ISCC
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006 A conf
Adaptive data placement in an embedded multiprocessor thread library.
DATE
Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan
2006 J jnl
Application-specific heterogeneous multiprocessor synthesis using extensible processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 Misc conf
Architectural support for safe software execution on embedded processors.
CODES+ISSS
Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006 — conf
Architectures for efficient face authentication in embedded systems.
DATE Designers' Forum
Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 A conf
Considering process variations during system-level power analysis.
ISLPED
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2006 J jnl
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 Misc conf
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.
VLSI Design
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 Misc conf
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
VLSI Design
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2006 A conf
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.
DATE
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2006 A ed.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006
ISLPED
Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu
2006 J jnl
RTL-Aware Cycle-Accurate Functional Power Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006 — conf
Safe Java Native Interface.
ISSSE
Gang Tan, Andrew W. Appel, Srimat Chakradhar, Anand Raghunathan, Srivaths Ravi, Daniel C. Wang
2006 — conf
Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
DATE Designers' Forum
Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2006 A* conf
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
DAC
Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2006 A* conf
Systematic software-based self-test for pipelined processors.
DAC
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
2006 J jnl
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2006 J jnl
The LOTTERYBUS on-chip communication architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
2006 J jnl
Use of Computation-Unit Integrated Memories in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005 B conf
Battery discharge characteristics of wireless sensor nodes: an experimental analysis.
SECON
Chulsung Park, Kanishka Lahiri, Anand Raghunathan
2005 A* conf
Efficient fingerprint-based user authentication for embedded systems.
DAC
Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005 — conf
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory.
CICC
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005 J jnl
Energy macromodeling of embedded operating systems.
ACM Trans. Embed. Comput. Syst.
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2005 Misc conf
Enhancing security through hardware-assisted run-time validation of program data properties.
CODES+ISSS
Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005 A* conf
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
DAC
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2005 J jnl
Generation of distributed logic-memory architectures through high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005 A conf
Hardware Accelerated Power Estimation.
DATE
Joel Coburn, Srivaths Ravi, Anand Raghunathan
2005 Misc conf
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.
VLSI Design
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2005 A* conf
Hybrid simulation for embedded software energy estimation.
DAC
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005 J jnl
Input space-adaptive optimization for embedded-software synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2005 Misc conf
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.
VLSI Design
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar
2005 A* conf
Power emulation: a new paradigm for power estimation.
DAC
Joel Coburn, Srivaths Ravi, Anand Raghunathan
2005 Misc conf
SECA: security-enhanced communication architecture.
CASES
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2005 A conf
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.
DATE
Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005 Misc conf
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.
VLSI Design
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004 J jnl
A hybrid energy-estimation technique for extensible processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004 — conf
An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software.
ESA/VLSI
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2004 A* conf
Automated energy/performance macromodeling of embedded software.
DAC
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2004 J jnl
Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
2004 J jnl
Custom-instruction synthesis for extensible-processor platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004 J jnl
Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
2004 J jnl
Design space exploration for optimizing on-chip communication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2004 J jnl
Efficient power profiling for battery-driven embedded system design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2004 Misc conf
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.
VLSI Design
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004 A conf
High-level synthesis using computation-unit integrated memories.
ICCAD
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004 J jnl
Input space adaptive design: a high-level methodology for optimizing energy and performance.
IEEE Trans. Very Large Scale Integr. Syst.
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2004 Misc conf
Power analysis of system-level on-chip communication architectures.
CODES+ISSS
Kanishka Lahiri, Anand Raghunathan
2004 A conf
Power estimation for cycle-accurate functional descriptions of hardware.
ICCAD
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004 Misc conf
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization.
VLSI Design
Weidong Wang, Anand Raghunathan, Niraj K. Jha
2004 J jnl
Resource budgeting for Multiprocess High-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey
2004 A* conf
Security as a new dimension in embedded system design.
DAC
Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
2004 J jnl
Security in embedded systems: Design challenges.
ACM Trans. Embed. Comput. Syst.
Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady
2004 Misc conf
Tamper Resistance Mechanisms for Secure, Embedded Systems.
VLSI Design
Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003 A conf
A Scalable Application-Specific Processor Synthesis Methodology.
ICCAD
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003 — conf
A comprehensive high-level synthesis system for control-flow intensive behaviors.
ACM Great Lakes Symposium on VLSI
Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha
2003 A* conf
A scalable software-based self-test methodology for programmable processors.
DAC
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
2003 J jnl
A simulation framework for energy-consumption analysis of OS-driven embedded applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2003 J jnl
Analysis of power dissipation in embedded systems using real-time operating systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2003 A conf
Analyzing the energy consumption of security protocols.
ISLPED
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003 Misc conf
Efficient RTL Power Estimation for Large Designs.
VLSI Design
Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003 Misc conf
Embedding Security in Wireless Embedded Systems.
VLSI Design
Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003 A conf
Energy Estimation for Extensible Processors.
DATE
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003 Misc conf
High-level Synthesis of Multi-process Behavioral Descriptions.
VLSI Design
Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey
2003 J jnl
High-level macro-modeling and estimation techniques for switching activity and power consumption.
IEEE Trans. Very Large Scale Integr. Syst.
Anand Raghunathan, Sujit Dey, Niraj K. Jha
2003 A conf
Securing Mobile Appliances: New Challenges for the System Designer.
DATE
Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
2003 — ch.
Software Architectural Transformations.
Embedded Software for SoC
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2003 A conf
Software Architectural Transformations: A New Approach to Low Energy Embedded Software.
DATE
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2003 A conf
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.
ICCAD
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003 A conf
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
DATE
Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
2002 — conf
Battery-efficient architecture for an 802.11 MAC processor.
ICC
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2002 A* conf
Communication architecture based power management for battery efficient system design.
DAC
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2002 J jnl
Communication-Based Power Management.
IEEE Des. Test Comput.
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2002 J jnl
Cosimulation-based power estimation for system-on-chip design.
IEEE Trans. Very Large Scale Integr. Syst.
Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
2002 C conf
Embedded Operating System Energy Analysis and Macro-Modeling.
ICCD
Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
2002 — conf
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
ASP-DAC/VLSI Design
Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
2002 — conf
FLEXBAR: A crossbar switching fabric with improved performance and utilization.
CICC
Jacob Chang, Srivaths Ravi, Anand Raghunathan
2002 — conf
Fast system-level power profiling for battery-efficient system design.
CODES
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2002 — conf
High-Level Synthesis with SIMD Units.
ASP-DAC/VLSI Design
Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac
2002 J jnl
High-level energy macromodeling of embedded software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2002 A conf
High-level synthesis of distributed logic-memory architectures.
ICCAD
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002 Misc conf
Innovations in Test Automation.
VTS
J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski
2002 — conf
Input Space Adaptive Embedded Software Synthesis.
ASP-DAC/VLSI Design
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2002 — conf
Optimizing public-key encryption for wireless clients.
ICC
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2002 — conf
Securing Wireless Data: System Architecture Challenges.
ISSS
Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi
2002 A conf
Synthesis of custom processors based on extensible platforms.
ICCAD
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002 A* conf
System design methodologies for a wireless security processing platform.
DAC
Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
2001 Misc conf
Accurate Power Macro-modeling Techniques for Complex RTL Circuits.
VLSI Design
Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
2001 Misc conf
Battery Life Estimation of Mobile Embedded Systems.
VLSI Design
Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
2001 Misc conf
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
VLSI Design
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2001 A* conf
High-level Software Energy Macro-modeling.
DAC
Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2001 A* conf
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.
DAC
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
2001 A* conf
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.
DAC
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
2001 Misc conf
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies.
VLSI Design
Anand Raghunathan, Sujit Dey
2001 J jnl
System-level performance analysis for designing on-chipcommunication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2001 A conf
Transient Power Management Through High Level Synthesis.
ICCAD
Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2000 J jnl
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.
IEEE Trans. Computers
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000 A* conf
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
DAC
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
2000 A conf
Efficient Exploration of the SoC Communication Architecture Design Space.
ICCAD
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2000 A conf
Efficient Power Co-Estimation Techniques for System-on-Chip Design.
DATE
Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
2000 J jnl
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
2000 Misc conf
Performance Analysis of Systems with Multi-Channel Communication Architectures.
VLSI Design
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2000 A* conf
Power analysis of embedded operating systems.
DAC
Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
1999 A* conf
Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
DAC
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
1999 J jnl
Controller-based power management for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
1999 A conf
Fast performance analysis of bus-based system-on-chip communication architectures.
ICCAD
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
1999 J jnl
Hierarchical test generation and design for testability methods for ASPPs and ASIPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1999 Misc conf
Low Power Design Methodologies for Systems-on-Chips.
VLSI Design
Kaushik Roy, Anand Raghunathan, Sujit Dey
1999 J jnl
Power management in high-level synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1999 J jnl
Register transfer level power optimization with emphasis on glitch analysis and reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Raghunathan, Sujit Dey, Niraj K. Jha
1999 C conf
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.
ICCD
Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya
1998 Misc conf
A Power Management Methodology for High-Level Synthesis.
VLSI Design
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1998 — conf
A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
CODES
Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
1998 J jnl
A design-for-testability technique for register-transfer level circuits using control/data flow extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1998 — conf
Considering Testability during High-level Design (Embedded Tutorial).
ASP-DAC
Sujit Dey, Anand Raghunathan, Rabindra K. Roy
1998 J jnl
Design for Testability Techniques at the Behavioral and Register-Transfer Levels.
J. Electron. Test.
Sujit Dey, Anand Raghunathan, Kenneth D. Wagner
1998 — book
High-Level Power Analysis and Optimization.
Anand Raghunathan, Niraj K. Jha, Sujit Dey
1998 A* conf
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.
DAC
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
1998 A conf
Transforming control-flow intensive designs to facilitate power management.
ICCAD
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
1998 A conf
Verification of RTL generated from scheduled behavior in a high-level synthesis flow.
ICCAD
Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama
1997 J jnl
Bottleneck removal algorithm for dynamic compaction in sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srimat T. Chakradhar, Anand Raghunathan
1997 J jnl
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1997 A* conf
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.
DAC
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1997 A* conf
Power Management Techniques for Control-Flow Intensive Designs.
DAC
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
1997 J jnl
SCALP: an iterative-improvement-based low-power data path synthesis system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Raghunathan, Niraj K. Jha
1996 A conf
A design for testability technique for RTL circuits using control/data flow extraction.
ICCAD
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1996 — conf
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.
FTCS
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
1996 A conf
Controller re-specification to minimize switching activity in controller/data path circuits.
ISLPED
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
1996 Misc conf
Dynamic test Sequence compaction for Sequential Circuits.
VLSI Design
Anand Raghunathan, Srimat T. Chakradhar
1996 A* conf
Glitch Analysis and Reduction in Register Transfer Level.
DAC
Anand Raghunathan, Sujit Dey, Niraj K. Jha
1996 A conf
Register-transfer level estimation techniques for switching activity and power consumption.
ICCAD
Anand Raghunathan, Sujit Dey, Niraj K. Jha
1995 A conf
Acceleration techniques for dynamic vector compaction.
ICCAD
Anand Raghunathan, Srimat T. Chakradhar
1995 C conf
An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation.
ISCAS
Anand Raghunathan, Niraj K. Jha
1995 A conf
An iterative improvement algorithm for low power data path synthesis.
ICCAD
Anand Raghunathan, Niraj K. Jha
1995 — conf
Bottleneck removal algorithm for dynamic compaction and test cycles reduction.
EURO-DAC
Srimat T. Chakradhar, Anand Raghunathan
1995 C conf
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
ICCD
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1995 Misc conf
Test generation for cyclic combinational circuits.
VLSI Design
Anand Raghunathan, Pranav Ashar, Sharad Malik
1995 J jnl
Test generation for cyclic combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anand Raghunathan, Pranav Ashar, Sharad Malik
1994 C conf
Behavioral Synthesis for low Power.
ICCD
Anand Raghunathan, Niraj K. Jha