Anand Bulusu - RankMe

59 papers C 5Misc 5Journal 16Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Hysteretic-Controlled Digital LDO Regulator for Enhanced Load Transient Response. SMACD Kartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu
2025	J	`jnl`	A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. IEEE Trans. Very Large Scale Integr. Syst. Mahipal Dargupally, Lomash Chandra Acharya, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
2025	—	`conf`	A Robust Fully Differential MAC Scheme Using Dummy Rows to Enhance the Signal Margin of Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Sudeb Dasgupta, Anand Bulusu
2025	—	`conf`	Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System. ISVLSI Neha Gupta, Lomash Chandra Acharya, Mahipal Dargupally, Khoirom Johnson Singh, Amit Kumar Behera, Johan Euphrosine, Sudeb Dasgupta, Anand Bulusu
2025	—	`conf`	Characterization of Inter-Chip Interconnects Using Piecewise Effective Capacitance. SMACD Nilotpal Sarma, Ashutosh Yadav, Sudeb Dasgupta, Anand Bulusu
2025	J	`jnl`	Robust and Reliable Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs Mahipal Dargupally, Lomash Chandra Acharya, Neha Gupta, Ahrron Kongala, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture. NewCAS Anmol Singla, Dinesh Kushwaha, Gulyawar Aman, Shubhradin Chakraborty, Abhishek Goel, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta
2024	J	`jnl`	Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	C	`conf`	SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	J	`jnl`	Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lomash Chandra Acharya, Arvind K. Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Neha Gupta, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures. APCCAS Sambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta
2023	—	`conf`	A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	A Novel Low-Power Shift-Register Controller for Digital Low-Dropout Regulators. APCCAS Kartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu
2023	—	`conf`	ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu
2023	J	`jnl`	Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
2023	Misc	`conf`	An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
2023	J	`jnl`	Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs. IEEE Trans. Circuits Syst. II Express Briefs Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Sudipto Chakraborty, Anand Bulusu
2023	C	`conf`	Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight. ISCAS Abhishek Acharya, Anand Bulusu
2023	J	`jnl`	Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. Microelectron. J. Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
2023	Misc	`conf`	Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. VLSID Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta
2022	C	`conf`	A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	—	`conf`	A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs. IEEE Trans. Circuits Syst. II Express Briefs Neeraj Mishra, Lalit Mohan Dani, Sudipto Chakraborty, Rajiv V. Joshi, Anand Bulusu
2022	Misc	`conf`	Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta
2022	—	`conf`	Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI. IRPS Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga, Avirup Dasgupta, Arnab Datta, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	C	`conf`	Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. ISCAS Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
2022	—	`conf`	Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. VDAT Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan
2021	J	`jnl`	An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lalit Mohan Dani, Neeraj Mishra, Anand Bulusu
2021	—	`conf`	Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain. VDAT Sarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, Anand Bulusu
2021	—	`conf`	Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm. ICM Ashutosh Yadav, Anand Bulusu, Sudeb Dasgupta, Surinder Singh
2021	C	`conf`	Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. ISCAS Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta
2021	—	`conf`	Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
2020	J	`jnl`	Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals. IEEE Trans. Circuits Syst. Neeraj Mishra, Lalit Dani, Kunal Sanvaniya, Sudeb Dasgupta, Sudipto Chakraborty, Anand Bulusu
2019	J	`jnl`	A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. IEEE Trans. Very Large Scale Integr. Syst. Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu
2019	J	`jnl`	An energy-efficient variation aware self-correcting latch. Microelectron. J. Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu
2019	J	`jnl`	High performance energy efficient radiation hardened latch for low voltage applications. Integr. Chaudhry Indra Kumar, Anand Bulusu
2018	—	`conf`	A modified method of logical effort for FinFET circuits considering impact of fin-extension effects. ISQED Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu
2018	—	`conf`	Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability. PRIME Chaudhry Indra Kumar, Anand Bulusu
2018	—	`conf`	UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective. PRIME Arvind Kumar Sharma, Naushad Alam, Anand Bulusu
2017	—	`conf`	Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. VDAT Satish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas
2016	—	`conf`	A novel energy-efficient self-correcting methodology employing INWE. SMACD Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
2016	—	`conf`	A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. VDAT Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas
2016	Misc	`conf`	FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSID Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
2016	—	`conf`	Lateral silicon nanowire based standard cell design for higher performance. APCCAS Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram
2015	—	`conf`	Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu
2014	Misc	`conf`	Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSID Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta
2013	J	`jnl`	Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron. J. Menka Yadav, Anand Bulusu, Sudeb Dasgupta
2012	—	`conf`	Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects. VDAT Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder
2011	—	`conf`	A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. ISVLSI Arnab Kumar Biswas, Anand Bulusu, Sudeb Dasgupta