An-Yeu Wu

188 papers A 1B 1C 18Misc 11Journal 102Unranked 55
YearRankTypeTitle / Venue / Authors
2026 J jnl
Efficient Coarse-to-Fine Diffusion Models with Time Step Sequence Redistribution.
CoRR
Yu-Shan Tai, An-Yeu Wu
2026 J jnl
PCG-Based Expectation Propagation Detector With Message-Passing Initialization and Approximated Variance for Fractional Doppler AFDM.
IEEE Wirel. Commun. Lett.
Chi-Wei Chen, Yi-Ming Lee, Shao-Chun Wang, Chun-Hsuan Kuo, An-Yeu Wu
2025 J jnl
EECS: Efficient End-Cloud Collaborative System With On-Demand Offloading Mechanism for Convolutional Neural Network.
IEEE Internet Things J.
Yi-Cheng Lo, Cheng-Lin Hsieh, Hao-Wei Chiang, An-Yeu Wu
2025 — conf
MPRDiff: Mixed Precision Restorative Diffusion Model with Incoherence Processing.
MLSP
Chih-Sheng Cheng, Yu-Shan Tai, An-Yeu Wu, Yen-Hsi Lee, Kai-Ya Wei
2025 — conf
Post-Training Quantization for Vision Mamba with K-Scaled Quantization and Reparameterization.
MLSP
Bo-Yun Shi, Yi-Cheng Lo, An-Yeu Wu, Yi-Min Tsai
2025 J jnl
Quick Bypass Mechanism of Zero-Shot Diffusion-Based Image Restoration.
CoRR
Yu-Shan Tai, An-Yeu Wu
2025 J jnl
Relay-Assisted Carrier Aggregation (RACA) Uplink System for Enhancing Data Rate of Extended Reality (XR).
IEEE Trans. Veh. Technol.
Chi-Wei Chen, Wen-Chiao Tsai, Lung-Sheng Tsai, An-Yeu Wu
2024 J jnl
BFP-CIM: Runtime Energy-Accuracy Scalable Computing-in-Memory-Based DNN Accelerator Using Dynamic Block-Floating-Point Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Cheng-Yang Chang, Chi-Tse Huang, Yu-Chuan Chuang, Kuang-Chao Chou, An-Yeu Wu
2024 A conf
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network.
DATE
Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu
2024 J jnl
Deep Unfolding-Based Channel Estimation for IRS-Aided mmWave Systems via Two-Stage LAMP Network With Row Compression.
IEEE Trans. Veh. Technol.
Wen-Chiao Tsai, Chi-Wei Chen, An-Yeu Wu
2024 J jnl
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning.
CoRR
Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Wu
2024 J jnl
Enhanced-GNN With Angular CSI for Beamforming Design in IRS-Assisted mmWave Communication Systems.
IEEE Commun. Lett.
Ting-Ju Yeh, Wen-Chiao Tsai, Chi-Wei Chen, An-Yeu Wu
2024 — conf
FQ4DM: Full Quantization for Diffusion Model.
MLSP
Chieh-En Wang, Yu-Shan Tai, An-Yeu Wu
2024 J jnl
LATTE: Low-Precision Approximate Attention with Head-wise Trainable Threshold for Efficient Transformer.
CoRR
Jiing-Ping Wang, Ming-Guang Lin, An-Yeu Wu
2024 J jnl
MPTQ-ViT: Mixed-PrecisionPost-TrainingQuantizationforVisionTransformer.
CoRR
Yu-Shan Tai, An-Yeu Wu
2024 J jnl
Quality-Aware Signal Processing Mechanism of PPG Signal for Long-Term Heart Rate Monitoring.
Sensors
Win-Ken Beh, Yu-Chia Yang, An-Yeu Wu
2023 J jnl
Dynamic-HDC: A Two-Stage Dynamic Inference Framework for Brain-Inspired Hyperdimensional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yu-Chuan Chuang, Cheng-Yang Chang, An-Yeu Wu
2023 J jnl
E-UPQ: Energy-Aware Unified Pruning-Quantization Framework for CIM Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Cheng-Yang Chang, Kuang-Chao Chou, Yu-Chuan Chuang, An-Yeu Wu
2023 C conf
H-RIS: Hybrid Computing-in-Memory Architecture Exploring Repetitive Input Sharing.
ISCAS
Yu-Chen Chen, Cheng-Yang Chang, An-Yeu Wu
2023 J jnl
Joint Optimization of Dimension Reduction and Mixed-Precision Quantization for Activation Compression of Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Shan Tai, Cheng-Yang Chang, Chieh-Fang Teng, Yi-Ta Chen, An-Yeu Wu
2023 J jnl
Noise-Level Aware Compressed Analysis Framework for Robust Electrocardiography Signal Monitoring.
IEEE J. Biomed. Health Informatics
Yi-Cheng Lo, Win-Ken Beh, Chiao-Chun Huang, An-Yeu Wu
2023 J jnl
Recent Progress and Development of Hyperdimensional Computing (HDC) for Edge Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Cheng-Yang Chang, Yu-Chuan Chuang, Chi-Tse Huang, An-Yeu Wu
2023 J jnl
Robust PPG-Based Mental Workload Assessment System Using Wearable Devices.
IEEE J. Biomed. Health Informatics
Win-Ken Beh, Yi-Hsuan Wu, An-Yeu Wu
2023 J jnl
S-QRD-ELM: Scalable QR-Decomposition-Based Extreme Learning Machine Engine Supporting Online Class-Incremental Learning for ECG-Based User Identification.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi-Ta Chen, Yu-Chuan Chuang, Li-Sheng Chang, An-Yeu Wu
2022 J jnl
An Effective Entropy-Assisted Mind-Wandering Detection System Using EEG Signals of MM-SART Database.
IEEE J. Biomed. Health Informatics
Yi-Ta Chen, Hsing-Hao Lee, Ching-Yen Shih, Zih-Ling Chen, Win-Ken Beh, Su-Ling Yeh, An-Yeu Wu
2022 — conf
C3-SL: Circular Convolution-Based Batch-Wise Compression for Communication-Efficient Split Learning.
MLSP
Cheng-Yen Hsieh, Yu-Chuan Chuang, An-Yeu Wu
2022 J jnl
C3-SL: Circular Convolution-Based Batch-Wise Compression for Communication-Efficient Split Learning.
CoRR
Cheng-Yen Hsieh, Yu-Chuan Chuang, An-Yeu Wu
2022 J jnl
D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Ming-Guang Lin, Chi-Tse Huang, Yu-Chuan Chuang, Yi-Ta Chen, Ying-Tuan Hsu, Yu-Kai Chen, Jyun-Jhe Chou, Tsung-Te Liu, Chi-Sheng Shih, An-Yeu Wu
2022 J jnl
Low-Complexity Compressive Channel Estimation for IRS-Aided mmWave Systems With Hypernetwork-Assisted LAMP Network.
IEEE Commun. Lett.
Wen-Chiao Tsai, Chi-Wei Chen, Chieh-Fang Teng, An-Yeu Wu
2022 J jnl
Low-Complexity Two-Step Optimization in Active-IRS-Assisted Uplink NOMA Communication.
IEEE Commun. Lett.
Chi-Wei Chen, Wen-Chiao Tsai, An-Yeu Wu
2022 — conf
T-EAP: Trainable Energy-Aware Pruning for NVM-based Computing-in-Memory Architecture.
AICAS
Cheng-Yang Chang, Yu-Chuan Chuang, Kuang-Chao Chou, An-Yeu Wu
2022 J jnl
WMMSE-Based Alternating Optimization for Low-Complexity Multi-IRS MIMO Communication.
IEEE Trans. Veh. Technol.
Chi-Wei Chen, Wen-Chiao Tsai, Sin-Sheng Wong, Chieh-Fang Teng, An-Yeu Wu
2021 J jnl
A 7.8-13.6 pJ/b Ultra-Low Latency and Reconfigurable Neural Network-Assisted Polar Decoder With Multi-Code Length Support.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chieh-Fang Teng, An-Yeu Wu
2021 C conf
A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification.
ISCAS
Cheng-Lin Lee, Yi-Ta Chen, An-Yeu Wu
2021 J jnl
A Tri-Mode Compressed Analytics Engine for Low-Power AF Detection With On-Demand EKG Reconstruction.
IEEE J. Solid State Circuits
Kuan-Chun Chen, Ching-Yao Chou, An-Yeu Wu
2021 J jnl
Compression-aware Projection with Greedy Dimension Reduction for Convolutional Neural Network Activations.
CoRR
Yu-Shan Tai, Chieh-Fang Teng, Cheng-Yang Chang, An-Yeu Wu
2021 J jnl
Two-Step Codebook-Assisted Alternating Minimization (CA-AltMin) for Low-Complexity Hybrid Beamforming Design.
IEEE Commun. Lett.
Sin-Sheng Wong, Chieh-Fang Teng, An-Yeu Wu
2020 J jnl
Accumulated Polar Feature based Deep Learning with Channel Compensation Mechanism for Efficient Automatic Modulation Classification under Time varying Channels.
CoRR
Chieh-Fang Teng, Ching-Yao Chou, Chun-Hsiang Chen, An-Yeu Wu
2020 J jnl
Accumulated Polar Feature-Based Deep Learning for Efficient and Lightweight Automatic Modulation Classification With Channel Compensation Mechanism.
IEEE Trans. Veh. Technol.
Chieh-Fang Teng, Ching-Yao Chou, Chun-Hsiang Chen, An-Yeu Wu
2020 J jnl
Neural Network-Aided BCJR Algorithm for Joint Symbol Detection and Channel Decoding.
CoRR
Wen-Chiao Tsai, Chieh-Fang Teng, Han-Mo Ou, An-Yeu Wu
2019 J jnl
A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring.
IEEE J. Solid State Circuits
Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu
2019 J jnl
AdaBoost-assisted Extreme Learning Machine for Efficient Online Sequential Classification.
CoRR
Yi-Ta Chen, Yu-Chuan Chuang, An-Yeu Wu
2019 J jnl
Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor.
IEEE Trans. Very Large Scale Integr. Syst.
Ding-Yuan Lee, Ching-Che Wang, An-Yeu Wu
2019 J jnl
Convolutional Neural Network-aided Bit-flipping for Belief Propagation Decoding of Polar Codes.
CoRR
Chieh-Fang Teng, Andrew Kuan-Shiuan Ho, Chen-Hsi Derek Wu, Sin-Sheng Wong, An-Yeu Wu
2019 J jnl
Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Ting-Sheng Chen, Kai-Ni Hou, Win-Ken Beh, An-Yeu Wu
2019 J jnl
Low-Complexity LSTM-Assisted Bit-Flipping Algorithm for Successive Cancellation List Polar Decoder.
CoRR
Chun-Hsiang Chen, Chieh-Fang Teng, An-Yeu Wu
2019 J jnl
Neural Network-based Equalizer by Utilizing Coding Gain in Advance.
CoRR
Chieh-Fang Teng, Han-Mo Ou, An-Yeu Wu
2019 J jnl
Real-Time Multi-User Detection Engine Design for IoT Applications via Modified Sparsity Adaptive Matching Pursuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ching-Chun Liao, Ting-Sheng Chen, An-Yeu Wu
2019 J jnl
Robust and Lightweight Ensemble Extreme Learning Machine Engine Based on Eigenspace Domain for Compressed Learning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Huai-Ting Li, Ching-Yao Chou, Yi-Ta Chen, Sheng-Hui Wang, An-Yeu Wu
2019 J jnl
Unsupervised Learning for Neural Network-based Polar Decoder via Syndrome Loss.
CoRR
Chieh-Fang Teng, An-Yeu Wu
2018 — conf
A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring.
ISSCC
Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu
2018 J jnl
Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing.
IEEE/ACM Trans. Netw.
Sheng-Chun Kao, Ding-Yuan Lee, Ting-Sheng Chen, An-Yeu Wu
2018 J jnl
Efficient Compressive Channel Estimation for Millimeter-Wave Large-Scale Antenna Systems.
IEEE Trans. Signal Process.
Cheng-Rung Tsai, Yu-Hsin Liu, An-Yeu Wu
2018 J jnl
Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals.
CoRR
Kuan Tung, Po-Kang Liu, Yu-Chuan Chuang, Sheng-Hui Wang, An-Yeu Wu
2018 J jnl
Low-Complexity Privacy-Preserving Compressive Analysis Using Subspace-Based Dictionary for ECG Telemonitoring System.
IEEE Trans. Biomed. Circuits Syst.
Ching-Yao Chou, En-Jui Chang, Huai-Ting Li, An-Yeu Wu
2018 Misc conf
Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving.
ICASSP
Kai-Ni Hou, Ting-Sheng Chen, Hung-Chi Kuo, Tzu-Hsuan Chen, An-Yeu Wu
2018 J jnl
Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism.
CoRR
Chieh-Fang Teng, Chen-Hsi Derek Wu, Andrew Kuan-Shiuan Ho, An-Yeu Wu
2018 J jnl
Polar Feature Based Deep Architectures for Automatic Modulation Classification Considering Channel Fading.
CoRR
Chieh-Fang Teng, Ching-Chun Liao, Chun-Hsiang Chen, An-Yeu Wu
2018 J jnl
Structured Random Compressed Channel Sensing for Millimeter-Wave Large-Scale Antenna Systems.
IEEE Trans. Signal Process.
Cheng-Rung Tsai, An-Yeu Wu
2017 J jnl
Compressive Sensing (CS) Assisted Low-Complexity Beamspace Hybrid Precoding for Millimeter-Wave MIMO Systems.
IEEE Trans. Signal Process.
Chiang-Hen Chen, Cheng-Rung Tsai, Yu-Hsin Liu, Wei-Lun Hung, An-Yeu Wu
2017 Misc conf
Compressive sensing based ECG monitoring with effective AF detection.
ICASSP
Hung-Chi Kuo, Yu-Min Lin, An-Yeu Wu
2017 J jnl
Low-Complexity Stochastic Gradient Pursuit Algorithm and Architecture for Robust Compressive Sensing Reconstruction.
IEEE Trans. Signal Process.
Yu-Min Lin, Yi Chen, Nai-Shan Huang, An-Yeu Wu
2017 — conf
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine.
VLSI-DAT
Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu
2017 — conf
Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems.
ASICON
En-Jui Chang, An-Yeu Wu
2017 J jnl
Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Huai-Ting Li, Ching-Yao Chou, Yuan-Ting Hsieh, Wei-Ching Chu, An-Yeu Wu
2016 J jnl
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu
2015 J jnl
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu-Min Lin, Huai-Ting Li, Ming-Han Chung, An-Yeu Wu
2015 — conf
Predicting stroke outcomes based on multi-modal analysis of physiological signals.
DSP
Pei-Wen Huang, Sung-Chun Tang, Yu-Min Lin, You-Cheng Liu, Wei-Jung Jou, Hsiao-I Jen, Dar-Ming Lai, An-Yeu Wu
2014 — conf
A stroke severity monitoring system based on quantitative modified multiscale entropy.
BioCAS
Wei-Jung Jou, Pei-Wen Huang, Yu-Min Lin, Sung-Chun Tang, Dar-Ming Lai, An-Yeu Wu
2014 C conf
High-throughput QC-LDPC decoder with cost-effective early termination scheme for non-volatile memory systems.
ISCAS
Yu-Min Lin, Yu-Hao Chen, Ming-Han Chung, An-Yeu Wu
2014 Misc conf
Hydra: An Energy-Efficient Programmable Cryptographic Coprocessor Supporting Elliptic-Curve Pairings over Fields of Large Characteristics.
IWSEC
Yun-An Chang, Wei-Chih Hong, Ming-Chun Hsiao, Bo-Yin Yang, An-Yeu Wu, Chen-Mou Cheng
2014 J jnl
Low-Complexity Motion-Compensated Beamforming Algorithm and Architecture for Synthetic Transmit Aperture in Ultrasound Imaging.
IEEE Trans. Signal Process.
Yu-Hao Chen, Yu-Min Lin, Kuan-Yu Ho, An-Yeu Wu, Pai-Chi Li
2014 J jnl
Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
En-Jui Chang, Hsien-Kai Hsin, Shu-Yen Lin, An-Yeu Wu
2014 J jnl
Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems.
IEEE Trans. Parallel Distributed Syst.
Hsien-Kai Hsin, En-Jui Chang, An-Yeu Wu
2013 Misc conf
Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems.
ICASSP
Ming-Han Chung, Yu-Min Lin, Cheng-Zhou Zhan, An-Yeu Wu
2013 — conf
Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems.
VLSI-DAT
Kun-Chih Chen, Shu-Yen Lin, An-Yeu Wu
2013 J jnl
Dual-Mode Low-Complexity Codebook Searching Algorithm and VLSI Architecture for LTE/LTE-Advanced Systems.
IEEE Trans. Signal Process.
Yi-Hsuan Lin, Yu-Hao Chen, Chun-Yuan Chu, Cheng-Zhou Zhan, An-Yeu Wu
2013 J jnl
Editorial: Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yen-Kuang Chen, An-Yeu Wu, Magdy A. Bayoumi, Farinaz Koushanfar
2013 — conf
Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems.
VLSI-DAT
Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang, Hsien-Kai Hsin, An-Yeu Wu
2013 J jnl
Implementation of ACO-Based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems.
IEEE Embed. Syst. Lett.
Hsien-Kai Hsin, En-Jui Chang, An-Yeu Wu
2013 J jnl
New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform.
IEEE Trans. Circuits Syst. II Express Briefs
Wen-Chung Shen, Hsiao-I Jen, An-Yeu Wu
2013 — conf
Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems.
ISSoC
Che-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, An-Yeu Wu
2013 J jnl
Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, An-Yeu Wu
2013 J jnl
Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems.
J. Signal Process. Syst.
Cheng-Hung Lin, Chun-Yu Chen, En-Jui Chang, An-Yeu Wu
2013 J jnl
Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit.
IEEE Trans. Very Large Scale Integr. Syst.
Chih-Hao Chao, Kun-Chih Chen, An-Yeu Wu
2013 J jnl
Securing M2M With Post-Quantum Public-Key Cryptography.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jie-Ren Shih, Yongbo Hu, Ming-Chun Hsiao, Ming-Shing Chen, Wen-Chung Shen, Bo-Yin Yang, An-Yeu Wu, Chen-Mou Cheng
2013 J jnl
Transport-layer-assisted routing for runtime thermal management of 3D NoC systems.
ACM Trans. Embed. Comput. Syst.
Chih-Hao Chao, Kun-Chih Chen, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu Wu
2012 — conf
Foreword.
VLSI-DAT
An-Yeu Wu, Li-C. Wang
2012 J jnl
Iterative Superlinear-Convergence SVD Beamforming Algorithm and VLSI Architecture for MIMO-OFDM Systems.
IEEE Trans. Signal Process.
Cheng-Zhou Zhan, Yen-Liang Chen, An-Yeu Wu
2012 J jnl
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders.
J. Signal Process. Syst.
Min-An Chao, Xin-Yu Shih, An-Yeu Wu
2012 J jnl
Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder.
J. Signal Process. Syst.
Chun-Yuan Chu, An-Yeu Wu
2012 — conf
Traffic-Balanced Topology-Aware Multiple Routing Adjustment for Throttled 3D NOC Systems.
SiPS
Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung, An-Yeu Wu
2012 — conf
Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems.
VLSI-DAT
Kun-Chih Chen, Chih-Hao Chao, Shu-Yen Lin, Hui-Shun Hung, An-Yeu Wu
2011 J jnl
A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks.
Des. Autom. Embed. Syst.
Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, An-Yeu Wu
2011 — conf
Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems.
SiPS
Cheng-Zhou Zhan, Zih-Ling Liu, An-Yeu Wu
2011 J jnl
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu
2011 — conf
Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon.
SoCC
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu
2011 J jnl
Multi-prediction particle filter for efficient parallelized implementation.
EURASIP J. Adv. Signal Process.
Chun-Yuan Chu, Chih-Hao Chao, Min-An Chao, An-Yeu Wu
2011 J jnl
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools.
J. Signal Process. Syst.
David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
2011 J jnl
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming.
J. Signal Process. Syst.
Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei-Kuan Shih, An-Yeu Wu
2011 — conf
Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems.
SoCC
Chih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu Wu
2010 — conf
A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system.
ESSCIRC
Yen-Liang Chen, Ting-Jyun Jheng, Cheng-Zhou Zhan, An-Yeu Wu
2010 J jnl
A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu
2010 J jnl
Generalized pipelined tomlinson-harashima precoder design methodology with build-in arbitrary speed-up factors.
IEEE Trans. Signal Process.
Yen-Liang Chen, An-Yeu Wu
2010 — conf
Regional ACO-based routing for load-balancing in NoC systems.
NaBIC
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, An-Yeu Wu
2010 — conf
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems.
NOCS
Chih-Hao Chao, Kai-Yuan Jheng, Haoyu Wang, Jia-Cheng Wu, An-Yeu Wu
2009 — conf
A 52-mW 8.29mm
ASP-DAC
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu
2009 — conf
A Channel-Adaptive Early Termination strategy for LDPC decoders.
SiPS
Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu
2009 C conf
A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems.
ISCAS
Shu-Yen Lin, Chan-Cheng Hsu, An-Yeu Wu
2009 C conf
A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM.
ISCAS
Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Wu
2009 J jnl
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
I-Chyn Wey, You-Gang Chen, Changhong Yu, An-Yeu Wu, Jie Chen
2009 J jnl
Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder.
IEEE Trans. Circuits Syst. I Regul. Pap.
Cheng-Hung Lin, Chun-Yu Chen, Tsung-Han Tsai, An-Yeu Wu
2009 J jnl
Multilevel LINC System Designs for Power Efficiency Enhancement of Transmitters.
IEEE J. Sel. Top. Signal Process.
Kai-Yuan Jheng, Yuan-Jyue Chen, An-Yeu Wu
2008 J jnl
An 8.29 mm
IEEE J. Solid State Circuits
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu
2008 C conf
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation.
ISCAS
Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu
2008 J jnl
Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme.
J. Signal Process. Syst.
Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu
2008 C conf
Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system.
ISCAS
Yen-Liang Chen, Cheng-Zhou Zhan, An-Yeu Wu
2008 J jnl
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
I-Chyn Wey, You-Gang Chen, An-Yeu Wu
2008 Misc conf
High-performance scheduling algorithm for partially parallel LDPC decoder.
ICASSP
Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu
2008 — conf
High-throughput dual-mode single/double binary map processor design for wireless wan.
SiPS
Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu
2008 — conf
Location-Constrained Particle Filter human positioning and tracking system.
SiPS
Chih-Hao Chao, Chun-Yuan Chu, An-Yeu Wu
2008 C conf
Low-power traceback MAP decoding for double-binary convolutional turbo decoder.
ISCAS
Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu
2008 J jnl
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks.
IEEE Trans. Computers
Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu Wu
2008 — conf
Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks.
SiPS
Ting-Jung Lin, Shu-Yen Lin, An-Yeu Wu
2008 J jnl
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel.
IEEE Trans. Very Large Scale Integr. Syst.
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
2007 — conf
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network.
NOCS
Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu
2007 C conf
A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance.
ISCAS
Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien
2007 J jnl
A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems.
IEEE Trans. Veh. Technol.
Jyh-Ting Lai, An-Yeu Wu, Wen-Chiang Chen
2007 — conf
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency.
SiPS
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
2007 C conf
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design.
ISCAS
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao
2007 J jnl
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee
2007 C conf
Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules.
ISCAS
Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu
2007 — conf
Multilevel Linc System Design for Power Efficiency Enhancement.
SiPS
Kai-Yuan Jheng, Yuan-Jyue Chen, An-Yeu Wu
2007 — conf
On the Fixed-Point Properties of Mixed-Scaling-Rotation Cordic Algorithm.
SiPS
Chi-Li Yu, Tzu-Hao Yu, An-Yeu Wu
2007 J jnl
On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold.
IEEE Trans. Signal Process.
Fan-Min Li, An-Yeu Wu
2007 — conf
Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems.
SiPS
Tzu-Hao Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, An-Yeu Wu
2007 — conf
Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems.
SiPS
Chun-Yuan Chu, Jyh-Ting Lai, An-Yeu Wu
2006 — conf
A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems.
SiPS
Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen
2006 — conf
A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold.
SiPS
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
2006 — conf
A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems.
SiPS
Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen
2006 — conf
A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System.
SiPS
Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, An-Yeu Wu
2006 C conf
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time.
ISCAS
Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
2006 C conf
A portable all-digital pulsewidth control loop for SOC applications.
ISCAS
Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
2006 J jnl
Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Huai-Yi Hsu, An-Yeu Wu, Jih-Chiang Yeo
2006 C conf
DSP engine design for LINC wireless transmitter systems.
ISCAS
Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao
2006 J jnl
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hsiu Lin, An-Yeu Wu, Fan-Min Li
2006 J jnl
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.
IEEE Trans. Very Large Scale Integr. Syst.
Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu
2006 — conf
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems.
SiPS
Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu
2006 — conf
Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems.
SiPS
Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, An-Yeu Wu
2005 — conf
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.
ISCAS (2)
I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu
2005 — conf
A memory-reduced log-MAP kernel for turbo decoder.
ISCAS (2)
Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu
2005 — conf
A scalable DCO design for portable ADPLL designs.
ISCAS (6)
Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
2005 — conf
Digital signal processing engine design for polar transmitter in wireless communication systems.
ISCAS (6)
Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu
2005 — conf
Low cost decision feedback equalizer (DFE) design for Giga-bit systems.
ICASSP (3)
Chih-Hsiu Lin, An-Yeu Wu
2005 J jnl
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chih-Hsiu Lin, An-Yeu Wu
2005 J jnl
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture.
IEEE Trans. Signal Process.
Chih-Hsiu Lin, An-Yeu Wu
2004 — conf
1000BASE-T Gigabit Ethernet baseband DSP IC design.
ISCAS (4)
Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu
2004 — conf
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code.
ISCAS (5)
Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu
2004 J jnl
Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique.
IEEE Trans. Circuits Syst. II Express Briefs
Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai
2004 J jnl
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai
2004 — conf
Least squares approximation-based ROM-free direct digital frequency synthesizer.
ISCAS (2)
Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu
2004 — conf
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP.
ISCAS (2)
Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu
2003 J jnl
A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm.
J. VLSI Signal Process.
Huai-Yi Hsu, Sheng-Feng Wang, An-Yeu Wu
2003 J jnl
A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes.
IEEE Trans. Circuits Syst. II Express Briefs
Cheng-Shing Wu, An-Yeu Wu, Chih-Hsiu Lin
2003 — conf
Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm.
ICASSP (2)
An-Yeu Wu, I-Hsien Lee, Cheng-Shing Wu
2003 J jnl
Editorial.
EURASIP J. Adv. Signal Process.
An-Yeu Wu, Ut-Va Koc, Keshab K. Parhi, Sergios Theodoridis
2003 — conf
Implementation of a programmable 64~2048-point FFT/IFFT processor for OFDM-based communication systems.
ISCAS (2)
Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu
2003 — conf
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-performance rotational operations.
ICASSP (2)
Zhi-Xiu Lin, An-Yeu Wu
2003 J jnl
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems.
EURASIP J. Adv. Signal Process.
Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, An-Yeu Wu
2002 J jnl
A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems.
EURASIP J. Adv. Signal Process.
Tsun-Shan Chan, Jen-Chih Kuo, An-Yeu Wu
2002 — conf
A new pipelined adaptive DFE architecture with improved convergence rate.
ISCAS (4)
Meng-Da Yang, An-Yeu Wu
2002 — conf
A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller.
ISCAS (5)
Cheng-Shing Wu, An-Yeu Wu
2001 — conf
A cost-effective TEQ algorithm for ADSL systems.
ICC
Chih-Chi Wang, An-Yeu Wu, Bor-Ming Wang
2001 Misc conf
A novel trellis-based searching scheme for EEAS-based CORDIC algorithm.
ICASSP
Cheng-Shing Wu, An-Yeu Wu
2001 Misc conf
A unified design framework for vector rotational CORDIC family based on angle quantization process.
ICASSP
An-Yeu Wu, Cheng-Shing Wu
2001 — conf
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter.
ISCAS (4)
Chi-Li Yu, An-Yeu Wu
2001 Misc conf
Cost-efficient multiplier-less FIR filter structure based on modified DECOR transformation.
ICASSP
I-Hsien Lee, Cheng-Shing Wu, An-Yeu Wu
2000 C conf
Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem.
ISCAS
Jye-Jong Leu, An-Yeu Wu
2000 C conf
Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT.
ISCAS
Cheng-Shing Wu, An-Yeu Wu
1999 Misc conf
A novel multirate adaptive FIR filtering algorithm and structure.
ICASSP
Cheng-Shing Wu, An-Yeu Wu
1998 J jnl
Algorithm-based low-power and high-performance multimedia signal processing.
Proc. IEEE
K. J. Ray Liu, An-Yeu Wu, Arun Raghupathy, Jie Chen
1998 J jnl
Algorithm-based low-power transform coding architectures: the multirate approach.
IEEE Trans. Very Large Scale Integr. Syst.
An-Yeu Wu, K. J. Ray Liu
1998 Misc conf
Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology.
ICASSP
An-Yeu Wu, Tsun-Shan Chan
1998 J jnl
System architecture of an adaptive reconfigurable DSP computing engine.
IEEE Trans. Circuits Syst. Video Technol.
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy
1995 Misc conf
Algorithm-based low-power transform coding architectures.
ICASSP
An-Yeu Wu, K. J. Ray Liu
1995 B conf
Parallel programmable video co-processor design.
ICIP
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu
1994 C conf
A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion.
ISCAS
An-Yeu Wu, K. J. Ray Liu
1993 C conf
A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation.
ISCAS
K. J. Ray Liu, An-Yeu Wu