Amitava Majumdar

30 papers A* 3A 2B 1C 5Misc 9Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2018	C	`conf`	Concurrent Sampling with Local Digitization - An Alternative to Analog Test Bus. ISCAS Nanqi Liu, Shravan K. Chaganti, Zhiqiang Liu, Degang Chen, Amitava Majumdar
2018	—	`conf`	Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. ATS Amitava Majumdar, Balakrishna Jayadev
2017	C	`conf`	A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection. ISCAS Zhiqiang Liu, Nanqi Liu, Shravan K. Chaganti, Degang Chen, Amitava Majumdar
2017	—	`conf`	Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. ATS Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin
2017	C	`conf`	Field profiling & monitoring of payload transistors in FPGAs. IOLTS Da Cheng, Amitava Majumdar, Xiaobao Wang, Nui Chong
2016	—	`conf`	Application debug in FPGAs in the presence of multiple asynchronous clocks. FPT Georgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar
2014	B	`conf`	Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies. ETS Richard Swanson, Anna Wong, Suraj Ethirajan, Amitava Majumdar
2014	Misc	`conf`	Hot topic session 9C: Test and fault tolerance for emerging memory technologies. VTS Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran
2014	Misc	`conf`	Innovative practices session 3C: Solving today's test challenges. VTS John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar
2014	Misc	`conf`	Innovative practices session 4C: Disruptive solutions in the non-digital world. VTS Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang
2012	Misc	`conf`	Power Characterization of Embedded SRAMs for Power Binning. VTS Yang Zhao, Lisa Grenier, Amitava Majumdar
2011	Misc	`conf`	A Novel mechanism for speed characterization during delay test. VTS Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou
2011	Misc	`conf`	Special session 5B: Panel How much toggle activity should we be testing with? VTS Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg
2009	Misc	`conf`	Panel: Analog Characterization and Test: The Long Road to Realization. VTS Arani Sinha, Amitava Majumdar, Vasu Ganti
2006	A*	`conf`	Hold time validation on silicon and the relevance of hazards in timing analysis. DAC Amitava Majumdar, Wei-Yu Chen, Jun Guo
2003	A	`conf`	Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. ITC Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan
2002	A	`conf`	A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC ITC Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar
2001	C	`conf`	Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
2000	J	`jnl`	Test-set partitioning for multi-weighted random LFSRs. Integr. Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar
1998	Misc	`conf`	Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. VTS Amitava Majumdar, Michio Komoda, Tim Ayres
1998	—	`conf`	On-Chip Test Embedding for Multi-Weighted Random LFSRs. DFT Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
1996	—	`conf`	Deterministic Test Pattern Reproduction by a Counter. ED&TC Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
1996	J	`jnl`	On the Use of Counters for Reproducing Deterministic Test Sets. IEEE Trans. Computers Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
1993	J	`jnl`	Probabilistic characterization of controllability in general homogeneous circuits. Comput. Aided Des. Amitava Majumdar, Sarma Sastry
1993	Misc	`conf`	Statistical Analysis of Controllability. VLSI Design Amitava Majumdar, Sarma Sastry
1992	A*	`conf`	On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. DAC Amitava Majumdar, Sarma Sastry
1991	A*	`conf`	A Branching Process Model for Observability Analysis of Combinational Circuits. DAC Sarma Sastry, Amitava Majumdar
1991	J	`jnl`	Test efficiency analysis of random self-test of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarma Sastry, Amitava Majumdar
1990	J	`jnl`	Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. IEEE Trans. Computers Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer
1988	C	`conf`	Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor. ICCD Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra