Amitabha Sinha

24 papers Journal 21Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations.
Int. J. Softw. Innov.
Atri Sanyal, Amitabha Sinha
2015 J jnl
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation.
CoRR
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury
2014 J jnl
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation.
SIGARCH Comput. Archit. News
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury
2013 J jnl
A Novel Reconfigurable Architecture of a DSP Processor for Efficient Mapping of DSP Functions using Field Programmable DSP Arrays.
CoRR
Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty
2013 J jnl
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays.
SIGARCH Comput. Archit. News
Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty
2013 J jnl
An integrated development platform of a reconfigurable radio processor for software defined radio.
SIGARCH Comput. Archit. News
Amrita Saha, Pijush Biswas, Amitabha Sinha
2013 J jnl
Design and simulation of MAC unit using combinational circuit and adder.
SIGARCH Comput. Archit. News
Subhashis Maitra, Amitabha Sinha
2013 J jnl
FPGA implementation of a novel DCT architecture reducing constant cosine terms.
SIGARCH Comput. Archit. News
Santanu Pal, Amitabha Sinha, Pijush Biswas
2013 J jnl
Field Programmable DSP Arrays - A
CoRR
Amitabha Sinha, Soumojit Acharyya, Suranjan Chakraborty, Mitrava Sarkar
2013 J jnl
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography.
SIGARCH Comput. Archit. News
Subhashis Maitra, Amitabha Sinha
2013 J jnl
High performance MAC unit for DSP and cryptographic applications.
SIGARCH Comput. Archit. News
Subhashis Maitra, Amitabha Sinha
2013 J jnl
Performance analysis of a FPGA based novel binary and DBNS multiplier.
SIGARCH Comput. Archit. News
Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha
2012 J jnl
"Floating point RNS": a new concept for designing the MAC unit of digital signal processor.
SIGARCH Comput. Archit. News
Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha
2012 — conf
A Scheme for Improving Bit Efficiency for Residue Number System.
ACITY (3)
Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha
2012 J jnl
A new algorithm for computing triple-base number system.
SIGARCH Comput. Archit. News
Subhashis Maitra, Amitabha Sinha
2012 J jnl
A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system.
SIGARCH Comput. Archit. News
Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha
2012 J jnl
Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System
CoRR
Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha
2012 J jnl
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT.
SIGARCH Comput. Archit. News
Nishant Kumar Giri, Amitabha Sinha
2011 J jnl
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique.
SIGARCH Comput. Archit. News
Satrughna Singha, Aniruddha Ghosh, Amitabha Sinha
2011 J jnl
Conversion of binary to single-term triple base numbers for DSP applications.
SIGARCH Comput. Archit. News
Anindita Chakraborty, Amitabha Sinha
2011 J jnl
High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA).
SIGARCH Comput. Archit. News
Malay Das, Amitabha Sinha, Nishant Kumar Giri
2010 J jnl
A novel architecture for conversion of binary to single digit double base numbers.
SIGARCH Comput. Archit. News
Manideepa Mukherjee, Amitabha Sinha
2010 — conf
A reconfigurable Digital Signal Processor using residue number system.
ISSPA
Sharbari Banerjee, Amitabha Sinha
2009 — conf
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio.
ICETC
Amrita Saha, Amitabha Sinha