Amit Narayan - RankMe

19 papers A* 2A 6B 2C 1Misc 2Journal 2Unranked 4

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	GridSpice: A Distributed Simulation Platform for the Smart Grid. IEEE Trans. Ind. Informatics Kyle Anderson, Jimmy Du, Amit Narayan, Abbas El Gamal
2006	J	`jnl`	Estimating and reducing the memory requirements of signal processing codes for embedded systems. IEEE Trans. Signal Process. J. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan, Ankush Agarwal
2005	A	`conf`	Steady-state analysis of voltage and current controlled oscillators. ICCAD Amit Mehrotra, Suihua Lu, David C. Lee, Amit Narayan
2004	B	`conf`	A Partitioning Methodology for BDD-Based Verification. FMCAD Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
2004	—	`conf`	Analysis techniques for obtaining the steady-state solution of MOS LC oscillators. ISCAS (5) Makram M. Mansour, Amit Mehrotra, William W. Walker, Amit Narayan
2004	—	`conf`	Continuation method in multitone harmonic balance. ISCAS (5) Suihua Lu, Amit Narayan, Amit Mehrotra
2003	—	`conf`	Improved Symbolic Verification Using Partitioning Techniques. CHARME Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain
2001	A*	`conf`	Reducing Memory Requirements of Nested Loops for Embedded Systems. DAC J. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan
1998	A	`conf`	Wireplanning in logic synthesis. ICCAD Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	C	`conf`	A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1997	Misc	`conf`	Formal Verification of Combinational Circuit. VLSI Design Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	Logic synthesis for large pass transistor circuits. ICCAD Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	Reachability analysis using partitioned-ROBDDs. ICCAD Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	Misc	`conf`	A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	Decomposition Techniques for Efficient ROBDD Construction. FMCAD Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
1996	A*	`conf`	Engineering Change in a Non-Deterministic FSM Setting. DAC Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	A	`conf`	Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1995	—	`conf`	Integrating Data Distribution and Loop Transformations. PP J. Ramanujam, Amit Narayan
1994	A	`conf`	Measurement and modeling of MOS transistor current mismatch in analog IC's. ICCAD Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli