Amit Golander

18 papers B 1Misc 8Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Accelerating AI through Novel Compute Architecture and Digital Photonic Gates.
SYSTOR
Fahim Bellan, Amit Golander
2025 Misc conf
Compute-based Fault Tolerance for DNN.
SYSTOR
Adi Molkho, Amit Golander, Oded Schwartz
2024 Misc conf
Cheap & Fast File-aaS for AI by Combining Scale-out Virtiofs, Block layouts and Delegations.
SYSTOR
Sagi Manole, Amit Golander
2023 Misc conf
Near-Memory Processing Offload to Remote (Persistent) Memory.
SYSTOR
Roei Kisous, Amit Golander, Yigal Korman, Tim Gubner, Rune Humborstad, Manyi Lu
2022 Misc conf
pmAddr: a persistent memory centric computing architecture.
SYSTOR
Amit Golander, Shai Taharlev, Yigal Korman
2018 Misc conf
Accelerating Unmodified Databases using Persistent Memory and Flash Storage Tiers.
SYSTOR
Amit Golander, Netanel Katzburg, Omer Zilberberg
2017 Misc conf
Persistent memory over fabric (PMoF).
SYSTOR
Amit Golander, Sagi Manole, Yigal Korman
2014 J jnl
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters.
IEEE Trans. Very Large Scale Integr. Syst.
Alexei Jolondz, Shlomo Weiss, Amit Golander
2014 J jnl
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators.
IEEE Trans. Computers
Sagi Manole, Amit Golander, Shlomo Weiss
2013 B conf
High Compression Rate and Ratio Using Predefined Huffman Dictionaries.
DCC
Amit Golander, Shai Tahar, Lior Glass, Giora Biran, Sagi Manole
2013 Misc conf
Leveraging predefined huffman dictionaries for high compression rate and ratio.
SYSTOR
Amit Golander, Shai Tahar, Lior Glass, Giora Biran, Sagi Manole
2011 J jnl
A Cost-Efficient L1-L2 Multicore Interconnect: Performance, Power, and Area Considerations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amit Golander, Nadav Levison, Omer Heymann, Alexander Briskman, Mark J. Wolski, Eric F. Robinson
2009 J jnl
Checkpoint allocation and release.
ACM Trans. Archit. Code Optim.
Amit Golander, Shlomo Weiss
2009 J jnl
Reexecution and Selective Reuse in Checkpoint Processors.
Trans. High Perform. Embed. Archit. Compil.
Amit Golander, Shlomo Weiss
2009 J jnl
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Amit Golander, Shlomo Weiss, Ronny Ronen
2008 J jnl
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals.
IEEE Comput. Archit. Lett.
Amit Golander, Shlomo Weiss, Ronny Ronen
2008 J jnl
Hiding the misprediction penalty of a resource-efficient high-performance processor.
ACM Trans. Archit. Code Optim.
Amit Golander, Shlomo Weiss
2008 — conf
Stateful hardware decompression in networking environment.
ANCS
Hao Yu, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass