Amit Chowdhary

15 papers A* 2A 3Misc 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2006 — conf
Effective linear programming based placement methods.
ISPD
Sherief Reda, Amit Chowdhary
2005 J jnl
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amit Chowdhary, John P. Hayes
2005 A* conf
How accurately can we model timing in a placement engine?
DAC
Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin
2003 A* conf
Force directed mongrel with physical net constraints.
DAC
Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin
2003 — conf
Timing driven force directed placement with physical net constraints.
ISPD
Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin
2002 J jnl
A Methodology for Synthesis of Data Path Circuitse.
IEEE Des. Test Comput.
Amit Chowdhary, Rajesh K. Gupta
2002 J jnl
General technology mapping for field-programmable gate arrays based on lookup tables.
ACM Trans. Design Autom. Electr. Syst.
Amit Chowdhary, John P. Hayes
1999 J jnl
Extraction of functional regularity in datapath circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
1998 A conf
A general approach for regularity extraction in datapath circuits.
ICCAD
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
1997 A conf
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs.
FPGA
Amit Chowdhary, John P. Hayes
1997 — —
Technology mapping for field-programmable gate arrays.
Amit Chowdhary
1996 J jnl
A Multi-Terminal Net Router for Field-Programmable Gate Arrays.
VLSI Design
Dinesh Bhatia, Amit Chowdhary
1995 A conf
Technology mapping for field-programmable gate arrays using integer programming.
ICCAD
Amit Chowdhary, John P. Hayes
1994 Misc conf
Detailed Routing of Multi-Terminal Nets in FPGAs.
VLSI Design
Amit Chowdhary, Dinesh Bhatia
1994 — conf
Mathematical model for routability analysis of FPGAs.
Great Lakes Symposium on VLSI
Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas