Amir Sabbagh Molahosseini

41 papers A 1C 2Journal 32Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Automatic residue-to-binary converter circuit generation and simplification using hybrid cartesian genetic programming and simulated annealing.
Expert Syst. Appl.
Amir Dadashzadeh, Mehdi Hosseizadeh, Amir Sabbagh Molahosseini, Amir Sahafi
2025 J jnl
Software-Defined Number Formats for High-Speed Belief Propagation.
IEEE Trans. Emerg. Top. Comput.
Amir Sabbagh Molahosseini, JunKyu Lee, Hans Vandierendonck
2024 J jnl
Application placement in fog-cum-cloud environment based on a low latency policy-making framework.
Clust. Comput.
Maryam Mirzapour-Moshizi, Vahid Sattari Naeini, Amir Sabbagh Molahosseini
2024 A conf
Exploiting Data Redundancy in CKKS Encoding for High-Speed Homomorphic Encryption.
AsiaCCS
Amir Sabbagh Molahosseini, Hans Vandierendonck
2023 J jnl
Resource-Efficient Convolutional Networks: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
ACM Comput. Surv.
JunKyu Lee, Lev Mukhanov, Amir Sabbagh Molahosseini, Umar Ibrahim Minhas, Yang Hua, Jesús Martínez del Rincón, Kiril Dichev, Cheol-Ho Hong, Hans Vandierendonck
2023 J jnl
uLog: a software-based approximate logarithmic number system for computations on SIMD processors.
J. Supercomput.
Saeedeh Jahanshahi, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi
2022 J jnl
A joint computational and resource allocation model for fast parallel data processing in fog computing.
J. Supercomput.
Mahmood Lakzaei, Vahid Sattari Naeini, Amir Sabbagh Molahosseini, Amir Javadpour
2022 J jnl
Hunter-prey optimization: algorithm and applications.
Soft Comput.
Iraj Naruei, Farshid Keynia, Amir Sabbagh Molahosseini
2022 J jnl
Image processing with high-speed and low-energy approximate arithmetic circuit.
Sustain. Comput. Informatics Syst.
Akram Mohammadi, Mokhtar Mohammadi Ghanatghestani, Amir Sabbagh Molahosseini, Yavar Safaei Mehrabani
2022 — ch.
Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific.
Approximate Computing
Amir Sabbagh Molahosseini, Leonel Sousa, Azadeh Alsadat Emrani Zarandi, Hans Vandierendonck
2022 J jnl
Zero-Aware Low-Precision RNS Scaling Scheme.
Axioms
Amir Sabbagh Molahosseini
2021 J jnl
A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set.
Comput. Sci.
Mohsen Mojahed, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi
2021 J jnl
A fault-tolerant architecture for internet-of-things based on software-defined networks.
Telecommun. Syst.
Katayoun Bakhshi Kiadehi, Amir Masoud Rahmani, Amir Sabbagh Molahosseini
2021 J jnl
Efficient Incorporation of the RNS Datapath in Reverse Converter.
IEEE Trans. Circuits Syst. II Express Briefs
MohammadReza Taheri, Amir Sabbagh Molahosseini, Keivan Navi
2021 J jnl
Increasing fault tolerance of data plane on the internet of things using the software-defined networks.
PeerJ Comput. Sci.
Katayoun Bakhshi Kiadehi, Amir Masoud Rahmani, Amir Sabbagh Molahosseini
2021 J jnl
Resource-Efficient Deep Learning: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
CoRR
JunKyu Lee, Lev Mukhanov, Amir Sabbagh Molahosseini, Umar Ibrahim Minhas, Yang Hua, Jesús Martínez del Rincón, Kiril Dichev, Cheol-Ho Hong, Hans Vandierendonck
2021 J jnl
Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration.
Comput. Electr. Eng.
Hoda Ghabeli, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2020 — conf
Half-Precision Floating-Point Formats for PageRank: Opportunities and Challenges.
HPEC
Amir Sabbagh Molahosseini, Hans Vandierendonck
2019 J jnl
Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding.
IEEE Trans. Very Large Scale Integr. Syst.
Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2019 J jnl
New energy-efficient hybrid wide-operand adder architecture.
IET Circuits Devices Syst.
Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2018 C conf
Towards Efficient Modular Adders based on Reversible Circuits.
ISCAS
Amir Sabbagh Molahosseini, Ailin Asadpoor, Azadeh Alsadat Emrani Zarandi, Leonel Sousa
2017 J jnl
A Multifunctional Unit for Designing Efficient RNS-Based Datapaths.
IEEE Access
Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Paulo Martins, Leonel Sousa
2017 J jnl
A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2
IEEE Trans. Circuits Syst. II Express Briefs
Seyed Mostafa Mirhosseini, Amir Sabbagh Molahosseini, Mehdi Hosseinzadeh, Leonel Sousa, Paulo Martins
2017 J jnl
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2
IEEE Trans. Very Large Scale Integr. Syst.
Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh
2017 J jnl
Residue-to-binary conversion for general moduli sets based on approximate Chinese remainder theorem.
Int. J. Comput. Math.
Nikolay I. Chervyakov, Amir Sabbagh Molahosseini, Pavel Alekseevich Lyakhov, Mikhail G. Babenko, Maxim Anatolievich Deryabin
2016 — conf
Area-delay-power-aware adder placement method for RNS reverse converter design.
LASCAS
Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Leonel Sousa, Mehdi Hosseinzadeh, Keivan Navi
2016 — conf
RNS reverse converters for moduli sets with dynamic ranges of 9n-bit.
LASCAS
Héctor Pettenghi, Roberto de Matos, Amir Sabbagh Molahosseini
2015 J jnl
Comparison of modular numbers based on the chinese remainder theorem with fractional values.
Autom. Control. Comput. Sci.
Nikolay I. Chervyakov, Amir Sabbagh Molahosseini, Pavel Alekseevich Lyakhov, Mikhail G. Babenko, Irina N. Lavrinenko, Anton V. Lavrinenko
2015 J jnl
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.
IEEE Trans. Very Large Scale Integr. Syst.
Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Mehdi Hosseinzadeh, Saeid Sorouri, Samuel Antão, Leonel Sousa
2014 — conf
Rethinking reverse converter design: From algorithms to hardware components.
ISIC
Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Seyed Mostafa Mirhosseini, Mehdi Hosseinzadeh
2012 J jnl
Efficient RNS to binary converters for the new 4-moduli set {2
IEICE Electron. Express
Mohammad Esmaeildoust, Keivan Navi, MohammadReza Taheri, Amir Sabbagh Molahosseini, Siavash Khodambashi
2011 J jnl
A General Reverse Converter Architecture with Low Complexity and High Performance.
IEICE Trans. Inf. Syst.
Keivan Navi, Mohammad Esmaeildoust, Amir Sabbagh Molahosseini
2011 J jnl
How to Teach Residue Number System to Computer Scientists and Engineers.
IEEE Trans. Educ.
Keivan Navi, Amir Sabbagh Molahosseini, Mohammad Esmaeildoust
2010 J jnl
A Reduced-Area Reverse Converter for the Moduli Set {2
Int. J. Adv. Comp. Techn.
Amir Sabbagh Molahosseini, M. Kuchaki Rafsanjani, S. H. Ghafouri, M. Hashemipour
2010 — conf
A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC.
ISVLSI
Amir Sabbagh Molahosseini, Keivan Navi
2010 C conf
A new four-modulus RNS to binary converter.
ISCAS
Amir Sabbagh Molahosseini, Faegheh Teymouri, Keivan Navi
2010 J jnl
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Amir Sabbagh Molahosseini, Keivan Navi, Chitra Dadkhah, Omid Kavehei, Somayeh Timarchi
2009 J jnl
A new five-moduli set for efficient hardware implementation of the reverse converter.
IEICE Electron. Express
Amir Sabbagh Molahosseini, Chitra Dadkhah, Keivan Navi
2009 J jnl
Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2
IEICE Trans. Inf. Syst.
Amir Sabbagh Molahosseini, Chitra Dadkhah, Keivan Navi, Mohammad Eshghi
2008 J jnl
An efficient architecture for designing reverse converters based on a general three-moduli set.
J. Syst. Archit.
Amir Sabbagh Molahosseini, Keivan Navi, Omid Hashemipour, Ali Jalali
2008 J jnl
An improved reverse converter for the moduli set {2
IEICE Electron. Express
Mehdi Hosseinzadeh, Amir Sabbagh Molahosseini, Keivan Navi