Amir M. Hajisadeghi

11 papers C 4Misc 1Journal 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits.
CoRR
Maryam Ghane, Amir M. Hajisadeghi, Hamid R. Zarandi
2024 J jnl
ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks.
CoRR
Ali Sedaghatgoo, Amir M. Hajisadeghi, Mahmoud Momtazpour, Nader Bagherzadeh
2024 J jnl
Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM.
Future Gener. Comput. Syst.
Amir M. Hajisadeghi, Mahmoud Momtazpour, Hamid R. Zarandi
2024 J jnl
Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM.
CoRR
Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour
2022 C conf
EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis.
DSD
Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi
2021 J jnl
CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics.
Microprocess. Microsystems
Amir M. Hajisadeghi, Hamid R. Zarandi
2020 J jnl
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories.
Microprocess. Microsystems
Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi
2019 Misc conf
A Fast and Efficient Fault Tree Analysis Using Approximate Computing.
EDCC
Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi, Saadat Pour-Mozafari
2018 C conf
A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays.
IOLTS
Hossein Bardareh, Amir M. Hajisadeghi, Hamid R. Zarandi
2018 C conf
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories.
DSD
Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi
2018 C conf
MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits.
DSD
Amir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi