Amir Kaivani

14 papers C 3Journal 9Unranked 2
YearRankTypeTitle / Venue / Authors
2016 J jnl
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation.
IEEE Trans. Very Large Scale Integr. Syst.
Amir Kaivani, Seok-Bum Ko
2014 J jnl
Area Efficient Sequential Decimal Fixed-point Multiplier.
J. Signal Process. Syst.
Liu Han, Amir Kaivani, Seok-Bum Ko
2014 C conf
High-speed FFT processors based on redundant number systems.
ISCAS
Amir Kaivani, Seok-Bum Ko
2013 J jnl
Decimal Division Algorithms: The Issue of Partial Remainders.
J. Signal Process. Syst.
Amir Kaivani, Seok-Bum Ko
2013 J jnl
Decimal SRT Square Root: Algorithm and Architecture.
Circuits Syst. Signal Process.
Amir Kaivani, Seok-Bum Ko
2013 — conf
Decimal signed digit addition using stored transfer encoding.
CCECE
Amir Kaivani, Seok-Bum Ko
2012 C conf
High-frequency sequential decimal multipliers.
ISCAS
Amir Kaivani, Li Chen, Seok-Bum Ko
2011 J jnl
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.
Comput. J.
Amir Kaivani, Ghassem Jaberipur
2011 J jnl
Improving the speed of decimal division.
IET Comput. Digit. Tech.
Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur
2010 J jnl
Fully redundant decimal addition and subtraction using stored-unibit encoding.
Integr.
Amir Kaivani, Ghassem Jaberipur
2009 J jnl
Improving the Speed of Parallel Decimal Multiplication.
IEEE Trans. Computers
Ghassem Jaberipur, Amir Kaivani
2007 J jnl
Binary-coded decimal digit multipliers.
IET Comput. Digit. Tech.
Ghassem Jaberipur, Amir Kaivani
2007 C conf
Reversible Barrel Shifters.
AICCSA
Saeid Gorgin, Amir Kaivani
2006 — conf
Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R.
ICIT
Amir Kaivani, Ali Zakerolhosseini, Saeid Gorgin, Mahmood Fazlali