Amer Baghdadi - RankMe

107 papers A* 4A 9B 3C 23Misc 1Journal 40Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Efficient Filter-Bank Pilot Structures for Multi-User Massive MIMO Systems. IEEE Trans. Commun. Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2025	J	`jnl`	Intrusion Detection on Resource-Constrained IoT Devices with Hardware-Aware ML and DL. CoRR Ali Diab, Adel Chehade, Edoardo Ragusa, Paolo Gastaldo, Rodolfo Zunino, Amer Baghdadi, Mostafa Rizk
2025	B	`conf`	Multi-Carrier MIMO Cognitive BackCom: Adaptive Processing with Temporal Combining Improved Data Stream Decoding. GLOBECOM Richard Boateng Nti, Derek Kwaku Pobi Asiedu, Amer Baghdadi, Samir Saoudi, Ji-Hoon Yun, Sébastien Roy
2024	J	`jnl`	Overlap-Save FBMC Receivers for Massive MIMO Systems. IEEE Trans. Wirel. Commun. Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2023	B	`conf`	Novel transmission technique based on intentional overlapping for spectral efficiency enhancement in multicarrier systems. PIMRC Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2022	J	`jnl`	A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping. J. Circuits Syst. Comput. Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
2022	C	`conf`	Enhancing embedded AI-based object detection using multi-view approach. RSP Zijie Ning, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet
2022	J	`jnl`	Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar Codes. IEEE Access Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi
2022	—	`conf`	Low Latency Architecture Design for Decoding 5G NR Polar Codes. DASIP Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi
2022	J	`jnl`	MOL-Based In-Memory Computing of Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Khaled Alhaj Ali, Amer Baghdadi, Elsa Dupraz, Mathieu Léonardon, Mostafa Rizk, Jean-Philippe Diguet
2022	C	`conf`	Marine Objects Detection Using Deep Learning on Embedded Edge Devices. RSP Dominique Heller, Mostafa Rizk, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet
2022	—	`conf`	On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes. ISIVC Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi
2022	—	`conf`	Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge Devices. ICECS 2022 Mostafa Rizk, Dominique Heller, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet
2022	—	`conf`	Overlap-Save FBMC receivers for massive MIMO systems under channel impairments. VTC Spring Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2022	—	`conf`	Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning. SYSINT Mostafa Rizk, Fatima Slim, Amer Baghdadi, Jean-Philippe Diguet
2021	J	`jnl`	Hardware Implementation of Overlap-Save-Based Fading Channel Emulator. IEEE Trans. Circuits Syst. II Express Briefs Muhammad Najam-ul-Islam, Muhammad Nauman, Atif Raza Jafri, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2021	—	`conf`	Low Complexity Non-binary Turbo Decoding based on the Local-SOVA Algorithm. ISTC Hugo Le Blevec, Rami Klaimi, Stefan Weithoffer, Charbel Abdel Nour, Amer Baghdadi
2021	J	`jnl`	NISC-Based MIMO MMSE Detector. J. Circuits Syst. Comput. Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Youssef Atat, Yasser Mohanna
2021	J	`jnl`	No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping. Des. Autom. Embed. Syst. Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
2021	J	`jnl`	Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA. IEEE Trans. Very Large Scale Integr. Syst. Jérémy Nadal, Amer Baghdadi
2020	C	`conf`	FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding. RSP Jérémy Nadal, Amer Baghdadi
2020	J	`jnl`	Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu
2020	C	`conf`	Memristor Overwrite Logic (MOL) for Energy-Efficient In-Memory DNN. ISCAS Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
2020	J	`jnl`	Overlap-Save FBMC Receivers. IEEE Trans. Wirel. Commun. Jérémy Nadal, François Leduc-Primeau, Charbel Abdel Nour, Amer Baghdadi
2019	J	`jnl`	Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection. J. Circuits Syst. Comput. Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
2019	—	`conf`	Crossbar Memory Architecture Performing Memristor Overwrite Logic. ICECS Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
2019	—	`conf`	MRL Crossbar-Based Full Adder Design. ICECS Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
2018	—	`conf`	A Block FBMC Receiver Designed for Short Filters. ICC Jérémy Nadal, François Leduc-Primeau, Charbel Abdel Nour, Amer Baghdadi
2018	J	`jnl`	Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. IEEE Access Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2018	—	`conf`	NISC Design Experience of Flexible Architectures for Digital Communication Applications. ICCA Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Ali Chamas Al Ghouwayel
2018	J	`jnl`	Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu
2018	J	`jnl`	Novel UF-OFDM Transmitter: Significant Complexity Reduction Without Signal Approximation. IEEE Trans. Veh. Technol. Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2018	C	`conf`	Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper. RSP Muhammad Waqas, Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam
2017	J	`jnl`	Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. CoRR Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2017	J	`jnl`	Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding. EURASIP J. Adv. Signal Process. Vianney Lapotre, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet
2017	J	`jnl`	Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping. EURASIP J. Embed. Syst. Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
2017	—	`conf`	Flexible hardware platform for demonstrating new 5G waveform candidates. ICM Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2017	J	`jnl`	Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD. IEEE Trans. Circuits Syst. II Express Briefs Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam, Michel Jézéquel
2017	J	`jnl`	High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards. IEEE Access Atif Raza Jafri, Amer Baghdadi, Muhammad Waqas, Muhammad Najam-ul-Islam
2017	—	`conf`	NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu
2017	—	`conf`	Reduced complexity FPGA implementation for UF-OFDM frequency domain transmitter. SiPS Said Medjkouh, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2017	—	`conf`	Towards memristor-based reconfigurable FFT architecture. ICM Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
2016	J	`jnl`	A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
2016	J	`jnl`	Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter. IEEE Trans. Circuits Syst. II Express Briefs Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
2015	C	`conf`	Caasper: providing accessible FPGA-acceleration over the network. RSP Valentin Mena Morales, Yahia Brakni, Pierre-Henri Horrein, Amer Baghdadi
2015	J	`jnl`	NISC-Based Soft-Input-Soft-Output Demapper. IEEE Trans. Circuits Syst. II Express Briefs Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
2015	J	`jnl`	Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst. Signal Process. Carlo Condo, Amer Baghdadi, Guido Masera
2014	C	`conf`	Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer. RSP Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
2014	A	`conf`	Energy-efficient FPGA implementation for binomial option pricing using OpenCL. DATE Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton
2014	J	`jnl`	Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. IET Commun. Carlo Condo, Amer Baghdadi, Guido Masera
2014	—	`conf`	UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN. ICECS Houcine Chougrani, Jean Schwoerer, Pierre-Henri Horrein, Amer Baghdadi, Francois Dehmas
2013	C	`conf`	A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. DSD Carlo Condo, Amer Baghdadi, Guido Masera
2013	—	`conf`	A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
2013	—	`conf`	An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet
2013	—	`conf`	Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization. ICCIT Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
2013	C	`conf`	Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
2013	A	`conf`	Parameterized area-efficient multi-standard turbo decoder. DATE Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
2013	C	`conf`	Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. RSP Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jézéquel
2013	A	`conf`	Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization. DATE Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohana, Youssef Atat
2013	C	`conf`	Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. DSD Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
2012	—	`conf`	Adaptive complexity MIMO turbo receiver applying turbo demodulation. ISTC Salim Haddad, Amer Baghdadi, Michel Jézéquel
2012	—	`conf`	An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. ReConFig Vianney Lapotre, Guy Gogniat, Jean-Philippe Diguet, Salim Haddad, Amer Baghdadi
2012	—	`conf`	Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm ISSoC Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel
2012	J	`jnl`	Complexity adaptive iterative receiver performing TBICM-ID-SSD. EURASIP J. Adv. Signal Process. Salim Haddad, Amer Baghdadi, Michel Jézéquel
2012	—	`conf`	Complexity reduction of shuffled parallel iterative demodulation with turbo decoding. ICT Salim Haddad, Oscar Sanchez, Amer Baghdadi, Michel Jézéquel
2012	C	`conf`	FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. RSP Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel
2012	J	`jnl`	Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy
2012	J	`jnl`	On the Convergence Speed of Turbo Demodulation With Turbo Decoding. IEEE Trans. Signal Process. Salim Haddad, Amer Baghdadi, Michel Jézéquel
2012	J	`jnl`	On the Convergence Speed of Turbo Demodulation with Turbo Decoding CoRR Salim Haddad, Amer Baghdadi, Michel Jézéquel
2011	A	`conf`	A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. DATE Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel
2011	A	`conf`	A low complexity stopping criterion for reducing power consumption in turbo decoders. DATE Pallavi Reddy, Fabien Clermidy, Amer Baghdadi, Michel Jézéquel
2011	C	`conf`	Area and throughput optimized ASIP for multi-standard turbo decoding. International Symposium on Rapid System Prototyping Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
2011	J	`jnl`	On chip interconnects for multiprocessor turbo decoding architectures. Microprocess. Microsystems Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi
2011	J	`jnl`	Parallel MIMO Turbo Equalization. IEEE Commun. Lett. Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
2011	Misc	`conf`	Reducing the number of iterations in iterative demodulation with turbo decoding. SoftCOM Salim Haddad, Amer Baghdadi, Michel Jézéquel
2010	J	`jnl`	Parallelism Efficiency in Convolutional Turbo Decoding. EURASIP J. Adv. Signal Process. Olivier Muller, Amer Baghdadi, Michel Jézéquel
2010	—	`conf`	Power consumption analysis and energy efficient optimization for turbo decoder implementation. SoC Pallavi Reddy, Fabien Clermidy, Rasheed Al Khayat, Amer Baghdadi, Michel Jézéquel
2010	C	`conf`	Rapid design and prototyping of universal soft demapper. ISCAS Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
2009	J	`jnl`	ASIP-Based Universal Demapper for Multiwireless Standards. IEEE Embed. Syst. Lett. Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
2009	A	`conf`	ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. DATE Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel
2009	C	`conf`	FPGA-based Radar Signal Processing for Automotive Driver Assistance System. IEEE International Workshop on Rapid System Prototyping Jean Saad, Amer Baghdadi, Frantz Bodereau
2009	C	`conf`	Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. DSD Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel
2009	J	`jnl`	From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. Olivier Muller, Amer Baghdadi, Michel Jézéquel
2009	C	`conf`	High-Level System Modeling for Rapid HW/SW Architecture Exploration. IEEE International Workshop on Rapid System Prototyping Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moenner, Renaud Pacalet
2009	C	`conf`	Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. IEEE International Workshop on Rapid System Prototyping Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
2008	C	`conf`	Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. ISCAS Hazem Moussa, Amer Baghdadi, Michel Jézéquel
2008	A*	`conf`	Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. DAC Hazem Moussa, Amer Baghdadi, Michel Jézéquel
2008	C	`conf`	From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. IEEE International Workshop on Rapid System Prototyping Olivier Muller, Amer Baghdadi, Michel Jézéquel
2007	A	`conf`	Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. DATE Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
2006	A	`conf`	ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. DATE Olivier Muller, Amer Baghdadi, Michel Jézéquel
2006	B	`conf`	On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. GLOBECOM Olivier Muller, Amer Baghdadi, Michel Jézéquel
2005	J	`jnl`	Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. Int. J. Embed. Syst. Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya
2004	J	`jnl`	A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. Ann. des Télécommunications Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya
2004	C	`conf`	An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. IEEE International Workshop on Rapid System Prototyping Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya
2004	A*	`conf`	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. DAC Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya
2003	C	`conf`	Embedded Application Prototyping on a Communication-Restricted Reconfigurable. IEEE International Workshop on Rapid System Prototyping Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya
2003	J	`jnl`	Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform. Des. Autom. Embed. Syst. Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya
2002	J	`jnl`	Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. IEEE Trans. Software Eng. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
2002	A*	`conf`	Component-based design approach for multicore SoCs. DAC Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava
2002	J	`jnl`	Exploration de l'espace des solutions architecturales dans le codesign. Tech. Sci. Informatiques Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
2002	—	`—`	Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC. (Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC). Amer Baghdadi
2001	—	`conf`	A generic wrapper architecture for multi-processor SoC cosimulation and design. CODES Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya
2001	A	`conf`	An efficient architecture model for systematic design of application-specific multiprocessor SoC. DATE Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2001	A*	`conf`	Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. DAC Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya
2000	C	`conf`	Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. IEEE International Workshop on Rapid System Prototyping Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya
2000	—	`conf`	Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. DIPES Nacer-Eddine Zergainoh, Amer Baghdadi, Ludovic Tambour, Damien Lyonnard, Lovic Gauthier, Ahmed Amine Jerraya
2000	—	`conf`	Generic Architecture Platform for Multiprocessor System-On-Chip Design. DIPES Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya