Amara Amara

59 papers A 3B 1C 13Journal 11Unranked 31
YearRankTypeTitle / Venue / Authors
2026 J jnl
CCSMRI: Circular compressed sensing MRI.
Biomed. Signal Process. Control.
Honggui Li, Dingtai Li, Sinan Chen, Nahid Md Lokman Hossain, Xinfeng Xu, Yuting Feng, Hantao Lu, Maria Trocan, Dimitri Galayko, Amara Amara, Mohamad Sawan
2025 J jnl
A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhongzhen Tong, Sifan Sun, Kaili Zhang, Chenghang Li, Jiye Yao, Yulong Qiu, Chao Wang, Zhaohao Wang, Ke Zhang, Amara Amara, Xiaoyang Lin, Weisheng Zhao
2025 C conf
ASP: A daptive Sparse LUT-based Bit-Slice Accelerator for Efficient CNN Inference.
ISCAS
Yueting Li, Yulong Qiu, Amara Amara
2022 — conf
Improving the quality of anthropometric measures during medical consultations with children aged under five years old in Burkina Faso.
BHI
Aziza Merzouki, Wessel Valkenburg, Marc Bayala, Maroussia Roelens, Olivia Keiser, Amara Amara
2022 J jnl
Predicting Feeding Conditions of Premature Infants Through Non-Nutritive Sucking Skills Using a Sensitized Pacifier.
IEEE Trans. Biomed. Eng.
Saeed Akbarzadeh, Tianchan Lyu, Roozbeh Farhoodi, Muhammad Awais, Saadullah Farooq Abbasi, Xian Zhao, Chen Chen, Amara Amara, Yasemin M. Akay, Metin Akay, Wei Chen
2022 J jnl
Real-Time and Cost-Effective Smart Mat System Based on Frequency Channel Selection for Sleep Posture Recognition in IoMT.
IEEE Internet Things J.
Haikang Diao, Chen Chen, Xiangyu Liu, Wei Yuan, Amara Amara, Toshiyo Tamura, Benny Lo, Jiahao Fan, Long Meng, Sio-Hang Pun, Yuan-Ting Zhang, Wei Chen
2021 J jnl
Deep Residual Networks for Sleep Posture Recognition With Unobtrusive Miniature Scale Smart Mat System.
IEEE Trans. Biomed. Circuits Syst.
Haikang Diao, Chen Chen, Wei Yuan, Amara Amara, Toshiyo Tamura, Jiahao Fan, Long Meng, Xiangyu Liu, Wei Chen
2021 — conf
Edge-Computing System Based on Smart Mat for Sleep Posture Recognition in IoMT.
MobiHealth
Haikang Diao, Chen Chen, Xiangyu Liu, Amara Amara, Wei Chen
2021 — conf
Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC.
MWSCAS
Navneet Gupta, Hitesh Shrimali, Adam Makosiej, Andrei Vladimirescu, Amara Amara
2021 C conf
Unobtrusive Smart Mat System for Sleep Posture Recognition.
ISCAS
Haikang Diao, Chen Chen, Wei Chen, Wei Yuan, Amara Amara
2019 C conf
ICTs as catalysts in child protection programmes: current landscape in South Asia & a concept to inform future use.
ICTD
Balwant Godara, Nihaalini Kumar, Frederique Boursin, Gatienne Jobit, Amara Amara, Thierry Agagliate
2019 — conf
Peer Networking and Capacity Building for Child Protection Professionals - Lessons from "ChildHub".
ICT4D (1)
Sendrine Constant, Balwant Godara, Thierry Agagliate, Nihaalini Kumar, Amara Amara
2017 — conf
1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell.
ESSCIRC
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2017 A conf
Tunnel FET based refresh-free-DRAM.
DATE
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2017 — conf
Tunnel FET based ultra-low-leakage compact 2T1C SRAM.
ISQED
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2016 — conf
0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus.
ISQED
Khaja Ahmad Shaik, Kiyoo Itoh, Amara Amara
2016 J jnl
0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Khaja Ahmad Shaik, Kiyoo Itoh, Amara Amara
2016 — conf
16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell.
ESSDERC
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2016 A conf
3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications.
DATE
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2016 C conf
A cost-effective approach for ubiquitous broadband access based on hybrid PLC-VLC system.
ISCAS
Jian Song, Sicong Liu, Guangxin Zhou, Bingyan Yu, Wenbo Ding, Fang Yang, Hongming Zhang, Xun Zhang, Amara Amara
2016 — conf
Cross entropy-based automatic thresholds setting-up method for sleep staging system.
BioCAS
Chen Chen, Adrien Ugon, Xun Zhang, Amara Amara, Patrick Garda, Jean-Gabriel Ganascia, Amina Kotti, Carole Philippe, Andréa Pinna
2016 — conf
Personalized sleep staging system using evolutionary algorithm and symbolic fusion.
EMBC
Chen Chen, Adrien Ugon, Xun Zhang, Amara Amara, Patrick Garda, Jean-Gabriel Ganascia, Carole Philippe, Andréa Pinna
2016 J jnl
Symbolic Fusion: A Novel Decision Support Algorithm for Sleep Staging Application.
EAI Endorsed Trans. Pervasive Health Technol.
Chen Chen, Xue Liu, Adrien Ugon, Xun Zhang, Amara Amara, Patrick Garda, Jean-Gabriel Ganascia, Carole Philippe, Andréa Pinna
2016 — conf
TFET NDR skewed inverter based sensing method.
NANOARCH
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana, Costin Anghel
2016 — conf
Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications.
ISQED
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2016 C conf
Ultra-compact SRAM design using TFETs for low power low voltage applications.
ISCAS
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel
2016 — conf
Uplink wireless transmission overview in bi-directional VLC systems.
ICECS
Pablo Perez-Nicoli, Fernando Silveira, Xun Zhang, Amara Amara
2015 C conf
0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell.
ISCAS
Kiyoo Itoh, Khaja Ahmad Shaik, Amara Amara
2015 — conf
Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology.
MIXDES
Amara Amara, Navneet Gupta, Khaja Ahmad Shaik, Costin Anghel, Kiyoo Itoh
2015 — conf
Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes.
IWASI
Andrei Vladimirescu, Costin Anghel, Amara Amara, Navneet Gupta, Adam Makosiej
2015 C conf
Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications.
ISCAS
Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel
2013 C conf
CMOS SRAM scaling limits under optimum stability constraints.
ISCAS
Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu
2012 C conf
A 32nm tunnel FET SRAM for ultra low leakage.
ISCAS
Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel
2012 — conf
Bipolar ReRAM Based non-volatile flip-flops for low-power architectures.
NEWCAS
Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Hraziia, Costin Anghel, Amara Amara
2012 — conf
Default connection in multi-electrode leads for cardiac pacemakers.
NEWCAS
Islam Seoudi, Jean-Francois Debroux, Marc Laflutte, Alaa Makdissi, Karima Amara, Renzo Dal Molin, Amara Amara
2012 A conf
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization.
DATE
Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara
2011 — conf
An Ultra-Low Power MAC Protocol for In-body Medical Implant Networks.
MobiHealth
Ashutosh Ghildiyal, Balwant Godara, Amara Amara
2011 — conf
Design of an ultra low power MAC for a heterogeneous in-body sensor network.
BODYNETS
Ashutosh Ghildiyal, Balwant Godara, Amara Amara
2011 — conf
Multi-electrode system for pacemaker applications.
ICECS
Islam Seoudi, Karima Amara, Fabrice Gayral, Renzo Dal Molin, Amara Amara
2010 C conf
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
ISCAS
Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Béranger, Marie-Anne Jaud, J. Dura, P. Perreau, Frédéric Boeuf, François Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Andrei Vladimirescu, Amara Amara
2010 — conf
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.
DELTA
Amara Amara, Bastien Giraud, Olivier Thomas
2010 J jnl
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.
J. Low Power Electron.
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
2009 — conf
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.
PATMOS
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
2009 C conf
SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch.
ISCAS
Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara
2008 C conf
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology.
ISCAS
Bastien Giraud, Amara Amara
2008 — conf
An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch.
ICECS
Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara
2008 — conf
Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.
DELTA
Bastien Giraud, Amara Amara
2007 C conf
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.
ISCAS
Bastien Giraud, Amara Amara, Andrei Vladimirescu
2006 — conf
A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors.
ICECS
Antoine Jalabert, Fabien Clermidy, Amara Amara
2006 — conf
Contribution of Custom Instructions on SoPC for iris recognition application.
ICECS
Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara
2006 J jnl
FPGA vs. ASIC for low power applications.
Microelectron. J.
Amara Amara, Frédéric Amiel, Thomas Ea
2005 — conf
Iris identification and robustness evaluation of a wavelet packets based algorithm.
ICIP (3)
Florence Rossant, Frédéric Amiel, Thomas Ea, Amara Amara, Manuel Torres Eslava
2005 — conf
Ultra low voltage design considerations of SOI SRAM memory cells.
ISCAS (4)
Olivier Thomas, Amara Amara
2004 B conf
IRIS features extraction using wavelet packets.
ICIP
Erik Rydgren, Thomas Ea, Frédéric Amiel, Florence Rossant, Amara Amara
2004 J jnl
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara
2004 J jnl
Systems-on-chip for telecommunications.
Ann. des Télécommunications
Jean-François Naviner, Amara Amara
2003 — conf
An SOI 4 transistors self-refresh ultra-low-voltage memory cell.
ISCAS (5)
Olivier Thomas, Amara Amara
2001 — conf
Static power consumption management in CMOS memories.
ISCAS (4)
Arnaud Turier, Lotfi Ben Ammar, Amara Amara
1996 — conf
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm.
Great Lakes Symposium on VLSI
Philippe Royannez, Amara Amara