Alvin M. Despain

68 papers A* 21A 6B 2C 2Journal 20Unranked 17

Year	Rank	Type	Title / Venue / Authors
2006	J	`jnl`	Design and evaluation of a hierarchical decoupled architecture. J. Supercomput. Won Woo Ro, Stephen P. Crago, Alvin M. Despain, Jean-Luc Gaudiot
2003	A	`conf`	HiDISC: A Decoupled Architecture for Data-Intensive Application. IPDPS Won Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain
2003	J	`jnl`	Position error signal estimation at high sampling rates using data and servo sector measurements. IEEE Trans. Control. Syst. Technol. Petros A. Ioannou, Elias B. Kosmatopoulos, Alvin M. Despain
2002	—	`conf`	Position error signal estimation at high sampling rates using data and servo sector measurements. CDC Petros A. loannou, Elias B. Kosmatopoulos, Alvin M. Despain
1998	J	`jnl`	Low-power state assignment targeting two- and multilevel logic implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1998	—	`conf`	Simulating the Effect of Decoherence and Inaccuracies on a Quantum Computer. QCQC Kevin M. Obenland, Alvin M. Despain
1997	J	`jnl`	Design and Simulation of the Aquarius-II Multiprocessor. J. Syst. Integr. Vason P. Srini, Tam M. Nguyen, Darren R. Busing, Michael J. Carlton, Bruce K. Holmer, Georges E. Smine, Alvin M. Despain
1997	J	`jnl`	State assignment based on two-dimensional placement and hypercube mapping. Integr. Shihming Liu, Massoud Pedram, Alvin M. Despain
1996	J	`jnl`	Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
1996	J	`jnl`	Design and Analysis of Hardware for High-Performance Prolog. J. Log. Program. Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Alvin M. Despain
1995	C	`conf`	190-MHz CMOS 4-Kbyte Pipelined Caches. ISCAS Apoorv Srivastava, Yong-Seon Koh, Barton Sano, Alvin M. Despain
1995	A*	`conf`	A Fast State Assignment Procedure for Large FSMs. DAC Shihming Liu, Massoud Pedram, Alvin M. Despain
1995	—	`conf`	Cache design trade-offs for power and performance optimization: a case study. ISLPD Ching-Long Su, Alvin M. Despain
1995	—	`conf`	Cache designs for energy efficiency. HICSS (1) Ching-Long Su, Alvin M. Despain
1995	C	`conf`	PLATO P: PLA Timing Optimization by Partitioning. ISCAS Shihming Liu, Massoud Pedram, Alvin M. Despain
1995	J	`jnl`	Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
1995	J	`jnl`	Synthesis of application specific instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ing-Jer Huang, Alvin M. Despain
1994	B	`conf`	A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel Processors. ICPADS Ching-Long Su, Chin-Chi Teng, Alvin M. Despain
1994	A*	`conf`	Branch with Masked Squashing in Superpipelined Processors. ISCA Ching-Long Su, Alvin M. Despain
1994	A*	`conf`	Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. DAC Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1994	A	`conf`	Generating instruction sets and microarchitectures from applications. ICCAD Ing-Jer Huang, Alvin M. Despain
1994	B	`conf`	Hardware-software co-designing benchmark-driven superpipelined instruction set processors. COMPSAC Ching-Long Su, Alvin M. Despain
1994	A	`conf`	Low power state assignment targeting two-and multi-level logic implementations. ICCAD Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
1994	—	`conf`	Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. COMPCON Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
1994	A*	`conf`	Minimizing branch misprediction penalties for superpipelined processors. MICRO Ching-Long Su, Alvin M. Despain
1994	J	`jnl`	Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1994	J	`jnl`	Saving Power in the Control Path of Embedded Processors. IEEE Des. Test Comput. Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
1994	A*	`conf`	Synthesis of Instruction Sets for Pipelined Microprocessors. DAC Ing-Jer Huang, Alvin M. Despain
1993	A*	`conf`	An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. MICRO Ing-Jer Huang, Alvin M. Despain
1993	A	`conf`	Efficient estimation of dynamic power consumption under a real delay model. ICCAD Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1993	A	`conf`	Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. ICCAD Ing-Jer Huang, Alvin M. Despain
1993	—	`conf`	PDAS: Processor design automation system. EURO-DAC Iksoo Pyo, Alvin M. Despain
1993	A*	`conf`	Prophetic branches: a branch architecture for code compaction and efficient execution. MICRO Apoorv Srivastava, Alvin M. Despain
1993	A*	`conf`	Technology Decomposition and Mapping Targeting Low Power Dissipation. DAC Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1993	A*	`conf`	The 16-fold way: a microparallel taxonomy. MICRO Barton Sano, Alvin M. Despain
1992	A*	`conf`	Application-Driven Design Automation for Microprocessor Design. DAC Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain
1992	A*	`conf`	High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. DAC Ing-Jer Huang, Alvin M. Despain
1992	J	`jnl`	High-Performance Logic Programming with the Aquarius Prolog Compiler. Computer Peter Van Roy, Alvin M. Despain
1991	A*	`conf`	AI and Design. IJCAI Saul Amarel, Alvin M. Despain, H. Penny Nii, Louis I. Steinberg, Marty Tenenbaum, Peter M. Will
1991	J	`jnl`	An integrated prolog architecture for symbolic and numeric executions. Ann. Math. Artif. Intell. Alvin M. Despain, Robert Yung
1991	A*	`conf`	Viewing Instruction Set Design as an Optimization Problem. MICRO Bruce K. Holmer, Alvin M. Despain
1990	A*	`conf`	Fast Prolog with an Extended General Purpose Architecture. ISCA Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry
1990	J	`jnl`	Scalable Shared-Memory Multiprocessor Architectures. Computer Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
1990	—	`conf`	The Aquarius IIU System. ICSI Darren R. Busing, Vason P. Srini, Georges E. Smine, Michael J. Carlton, Alvin M. Despain
1990	—	`conf`	The Benefits of Global Dataflow Analysis for an Optimizing Prolog Compiler. NACLP Peter Van Roy, Alvin M. Despain
1990	J	`jnl`	The Performance of Parallel Prolog Programs. IEEE Trans. Computers Barry S. Fagin, Alvin M. Despain
1988	A	`conf`	A two-tier memory architecture for high-performance multiprocessor systems. ICS Tam M. Nguyen, Vason P. Srini, Alvin M. Despain
1988	—	`conf`	Prolog at Berkeley. COMPCON Alvin M. Despain
1987	—	`conf`	An Empirical Study of the Warren Abstract Machine. SLP Hervé J. Touati, Alvin M. Despain
1987	J	`jnl`	Aquarius. SIGARCH Comput. Archit. News Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy
1987	—	`conf`	Experience with Prolog as a Hardware Specification Language. SLP William R. Bush, Gino Cheng, Patrick C. McGeer, Alvin M. Despain
1987	A*	`conf`	Performance Studies of a Parallel Prolog Architecture. ISCA Barry S. Fagin, Alvin M. Despain
1986	A*	`conf`	Delay reduction using simulated annealing. DAC Jonathan D. Pincus, Alvin M. Despain
1986	—	`conf`	High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation. COMPCON Alvin M. Despain, Yale N. Patt, Tep P. Dobry, Jung-Herng Chang, Wayne Citrin
1986	A*	`conf`	Multiprocessor Cache Synchronization: Issues, Innovations, Evolution. ISCA Philip Bitar, Alvin M. Despain
1985	—	`conf`	AND-Parallelism of Logic Programs Based on a Static Data Dependency Analysis. COMPCON Jung-Herng Chang, Alvin M. Despain, Doug DeGroot
1985	—	`conf`	Aquarius - A High Performance Computing System for Symbolic/Numeric Applications. COMPCON Alvin M. Despain, Yale N. Patt
1985	A*	`conf`	Compiling Prolog into microcode: a case study using the NCR/32-000. MICRO Barry S. Fagin, Yale N. Patt, Vason P. Srini, Alvin M. Despain
1985	J	`jnl`	Fast fourier transform processors using Gaussian residue arithmetic. J. Parallel Distributed Comput. Alvin M. Despain, Allen M. Peterson, Oscar S. Rothaus, Erling Wold
1985	A*	`conf`	Performance Studies of a Prolog Machine Architecture. ISCA Tep P. Dobry, Alvin M. Despain, Yale N. Patt
1985	—	`conf`	Semi-Intelligent Backtracking of Prolog Based on Static Data Dependency Analysis. SLP Jung-Herng Chang, Alvin M. Despain
1984	A*	`conf`	Design decisions influencing the microarchitecture for a Prolog machine. MICRO Tep P. Dobry, Yale N. Patt, Alvin M. Despain
1984	J	`jnl`	Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations. IEEE Trans. Computers Erling Wold, Alvin M. Despain
1984	—	`conf`	The Aquarius Project. COMPCON Alvin M. Despain, Yale N. Patt
1979	J	`jnl`	Very Fast Fourier Transform Algorithms Hardware for Implementation. IEEE Trans. Computers Alvin M. Despain
1978	—	`conf`	Communication In X-TREE, A Modular Multiprocessor System. ACM Annual Conference (1) Carlo H. Séquin, Alvin M. Despain, David A. Patterson
1978	A*	`conf`	X-Tree: A Tree Structured Multi-Processor Computer Architecture. ISCA Alvin M. Despain, David A. Patterson
1974	J	`jnl`	Fourier Transform Computers Using CORDIC Iterations. IEEE Trans. Computers Alvin M. Despain