Alvin Leng Sun Loke

14 papers Misc 1Journal 4Unranked 9

Year	Rank	Type	Title / Venue / Authors
2023	Misc	`conf`	Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits. VLSID Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi, Gaurav Agrawal, Krishna Thakur, Deependra Kumar Jain, Alvin Leng Sun Loke, Atul Kumar, Manish Kumar Upadhyay, Bhawna, Sanjoy Kumar Dey
2020	—	`conf`	A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. VLSI Circuits Wei-Chih Chen, Chin-Hua Wen, Chin-Ming Fu, Tsung-Hsien Tsai, Yu-Chi Chen, Wen-Hung Huang, Chien-Chun Tsai, Alvin Leng Sun Loke, C. H. Kenny
2020	—	`conf`	Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. VLSI Circuits Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen
2019	—	`conf`	Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. CICC Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary
2019	—	`conf`	Nanoscale CMOS Implications on Analog/Mixed-Signal Design. CICC Alvin Leng Sun Loke, C. K. Lee, Burton Mike Leary
2018	—	`conf`	Analog/mixed-signal design challenges in 7-nm CMOS and beyond. CICC Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary
2012	J	`jnl`	An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. IEEE J. Solid State Circuits Alvin Leng Sun Loke, Bruce Andrew Doyle, Sanjeev K. Maheshwari, Dennis Michael Fischette, Charles Lin Wang, Tin Tin Wee, Emerson S. Fang
2012	J	`jnl`	Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Hasnain Lakdawala, Alvin Leng Sun Loke
2011	—	`conf`	Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. A-SSCC Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang
2010	—	`conf`	A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. ISSCC Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang
2010	J	`jnl`	An Embedded All-Digital Circuit to Measure PLL Response. IEEE J. Solid State Circuits Dennis Michael Fischette, Alvin Leng Sun Loke, Richard Joseph DeSantis, Gerry R. Talbot
2009	—	`conf`	Loopback architecture for wafer-level at-speed testing of embedded HyperTransport CICC Alvin Leng Sun Loke, Bruce Andrew Doyle, Michael M. Oshima, Wade L. Williams, Robert G. Lewis, Charles Lin Wang, Audie Hanpachern, Karen M. Tucker, Prashanth Gurunath, Gladney C. Asada, Chad O. Lackey, Tin Tin Wee, Emerson S. Fang
2006	J	`jnl`	A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. IEEE J. Solid State Circuits Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Michael J. Gilsdorf
2005	—	`conf`	A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking. CICC Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf