Alpana Agarwal

24 papers Misc 1Journal 20Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
A low power SAR ADC with fine-tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS.
Integr.
Naveen Kandpal, Anil Singh, Alpana Agarwal
2024 J jnl
An artificial intelligence-based 4-to-10-bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate.
Int. J. Circuit Theory Appl.
Naveen Kandpal, Anil Singh, Alpana Agarwal
2024 J jnl
Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology.
J. Circuits Syst. Comput.
Abhishek Mishra, Anil Singh, Alpana Agarwal
2022 J jnl
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.
Circuits Syst. Signal Process.
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
2022 J jnl
A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range.
Circuits Syst. Signal Process.
Naveen Kandpal, Anil Singh, Alpana Agarwal
2022 J jnl
A Scalable Fully-Digital Differential Analog Voltage Comparator.
J. Circuits Syst. Comput.
Ashima Gupta, Anil Singh, Alpana Agarwal
2022 J jnl
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator.
Int. J. Circuit Theory Appl.
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
2022 J jnl
Functional validation of highly synthesizable voltage comparator on FPGA.
Integr.
Ashima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal
2022 J jnl
Intra and inter-patient arrhythmia classification using feature fusion with novel feature set based on fractional-order and fibonacci series.
Biomed. Signal Process. Control.
Amandeep Kaur, Sanjay Kumar, Ravinder Agarwal, Alpana Agarwal
2021 J jnl
Bidirectional transfer learning model for sentiment analysis of natural language.
J. Ambient Intell. Humaniz. Comput.
Shivani Malhotra, Vinay Kumar, Alpana Agarwal
2021 J jnl
Entropy optimized semi-supervised decomposed vector-quantized variational autoencoder model based on transfer learning for multiclass text classification and generation.
CoRR
Shivani Malhotra, Vinay Kumar, Alpana Agarwal
2020 J jnl
A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.
J. Circuits Syst. Comput.
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
2020 J jnl
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology.
J. Circuits Syst. Comput.
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
2020 J jnl
An Efficient R-Peak Detection Using Riesz Fractional-Order Digital Differentiator.
Circuits Syst. Signal Process.
Amandeep Kaur, Sanjay Kumar, Alpana Agarwal, Ravinder Agarwal
2020 J jnl
Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC.
J. Circuits Syst. Comput.
Ashima Gupta, Anil Singh, Alpana Agarwal
2019 — conf
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems.
IntelliSys (1)
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
2019 J jnl
Fast digital foreground gain error calibration for pipelined ADC.
IET Circuits Devices Syst.
Jupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal
2019 J jnl
Highly-digital voltage scalable 4-bit flash ADC.
IET Circuits Devices Syst.
Ashima Gupta, Anil Singh, Alpana Agarwal
2017 J jnl
A Digital-Based Low-Power Fully Differential Comparator.
J. Circuits Syst. Comput.
Anil Singh, Ayushi Goel, Alpana Agarwal
2017 J jnl
Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology.
IET Circuits Devices Syst.
Anil Singh, Veena Rawat, Alpana Agarwal
2013 — conf
A Combined CMOS Reference Circuit with Supply and Temperature Compensation.
VDAT
Madhusoodan Agrawal, Alpana Agarwal
2011 — conf
Synthesis of Analog IC Building Blocks.
ISVLSI
Alpana Agarwal, Chandra Shekhar
2008 J jnl
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers.
VLSI Design
Alpana Agarwal, Chandra Shekhar
2004 Misc conf
Carry Circuitry for LUT-Based FPGA.
VLSI Design
Varun Jindal, Alpana Agarwal