Allen C.-H. Wu

68 papers A* 5A 15C 2Journal 24Unranked 21

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. ACM Trans. Design Autom. Electr. Syst. Cheng-Hsien Lin, Kuan-Ting Chen, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2021	—	`conf`	A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). ASP-DAC Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
2021	J	`jnl`	A novel privacy-preserving deep learning scheme without a cryptography component. Comput. Electr. Eng. Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
2019	J	`jnl`	A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. CoRR Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
2019	—	`conf`	Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang
2019	—	`conf`	Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. SoCC Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
2017	J	`jnl`	A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2016	A	`conf`	A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2015	—	`conf`	Elastylus: flexible haptic painting stylus. SIGGRAPH Asia Emerging Technologies Ruimin Lyu, Haojie Hao, Wei Chen, Yuan Liu, Feng Wang, Allen C.-H. Wu
2007	J	`jnl`	Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
2006	J	`jnl`	A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. Very Large Scale Integr. Syst. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2006	J	`jnl`	Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2006	C	`conf`	Performance-driven crosstalk elimination at post-compiler level. ISCAS Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
2005	—	`conf`	A fast lane and vehicle detection approach for autonomous vehicles. SIP Bing-Fei Wu, Chuan-Tsai Lin, Chao-Jung Chen, Tze-Chiuan Lai, Hsueh-Lung Liao, Allen C.-H. Wu
2005	—	`conf`	A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2004	A	`conf`	Decomposition of Instruction Decoder for Low Power Design. DATE Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
2003	A	`conf`	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
2003	A	`conf`	G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
2002	—	`conf`	A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. ISCAS (1) M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu
2002	—	`conf`	High-performance FIR generation based on a timing-driven architecture and component selection method. ISCAS (4) Jerry C.-Y. Kao, C.-F. Su, Allen C.-H. Wu
2001	—	`conf`	An RTL design-space exploration method for high-level applications. ASP-DAC Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu
2000	J	`jnl`	A predictive system shutdown method for energy saving of event-driven computation. ACM Trans. Design Autom. Electr. Syst. Chi-Hong Hwang, Allen C.-H. Wu
2000	A	`conf`	Delay Budgeting for a Timing-Closure-Driven Design Method. ICCAD Chien-Chu Kuo, Allen C.-H. Wu
2000	—	`conf`	Embedded tutorial: essential issues for IP reuse. ASP-DAC Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud
2000	J	`jnl`	Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. Very Large Scale Integr. Syst. Allen C.-H. Wu, Nikil D. Dutt
2000	J	`jnl`	Multiway FPGA partitioning by fully exploiting design hierarchy. ACM Trans. Design Autom. Electr. Syst. Wen-Jong Fang, Allen C.-H. Wu
1999	—	`conf`	A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ASP-DAC Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu
1999	A*	`conf`	A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1999	J	`jnl`	A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1999	J	`jnl`	EmGen-a module generator for logic emulation applications. IEEE Trans. Very Large Scale Integr. Syst. Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
1999	A	`conf`	Module Generation of High Performance FPGA-Based Multipliers. FPGA Kun-Ming Ho, Allen C.-H. Wu
1998	J	`jnl`	Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. IEEE Des. Test Comput. Wen-Jong Fang, Allen C.-H. Wu
1998	A*	`conf`	Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. DAC Wen-Jong Fang, Allen C.-H. Wu
1998	—	`conf`	Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
1997	A*	`conf`	A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. DAC Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen
1997	J	`jnl`	A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wen-Jong Fang, Allen C.-H. Wu
1997	J	`jnl`	A performance and routability-driven router for FPGAs considering path delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuh-Sheng Lee, Allen C.-H. Wu
1997	A	`conf`	A predictive system shutdown method for energy saving of event-driven computation. ICCAD Chi-Hong Hwang, Allen C.-H. Wu
1997	—	`conf`	An entropy measure for power estimation of Boolean functions. ASP-DAC Chi-Hong Hwang, Allen C.-H. Wu
1997	—	`conf`	DP-Gen: a datapath generator for multiple-FPGA applications. ASP-DAC Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin
1997	J	`jnl`	Datapath Optimization Using Layout Information: An Empirical Study. VLSI Design Allen C.-H. Wu
1997	—	`conf`	Evaluating cost-performance tradeoffs for system level applications. ASP-DAC Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu
1997	A	`conf`	Module Generation of Complex Macros for Logic-Emulation Applications. FPGA Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
1997	A*	`conf`	Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. DAC Wen-Jong Fang, Allen C.-H. Wu
1997	—	`conf`	Preserving HDL synthesis hierarchy for cell placement. ISPD Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
1997	J	`jnl`	Scheduling techniques for variable voltage low power designs. ACM Trans. Design Autom. Electr. Syst. Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu
1996	A	`conf`	A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. ICCAD Wen-Jong Fang, Allen C.-H. Wu
1996	J	`jnl`	The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. Softw. Pract. Exp. Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu
1995	A*	`conf`	A Performance and Routability Driven Router for FPGAs Considering Path Delays. DAC Yuh-Sheng Lee, Allen C.-H. Wu
1995	J	`jnl`	Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1995	—	`conf`	EMPAR: an interactive synthesis environment for hardware emulations. ASP-DAC Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee
1995	J	`jnl`	High-Level Synthesis -A Tutorial. IEICE Trans. Inf. Syst. Allen C.-H. Wu, Youn-Long Lin
1995	J	`jnl`	TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
1994	—	`conf`	A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin
1994	J	`jnl`	A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
1994	C	`conf`	State Assignment for Power and Area Minimization. ICCD Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1993	A	`conf`	Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1992	A	`conf`	Accurate layout area and delay modeling for system level design. ICCAD Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
1992	A	`conf`	An effective methodology for functional pipelining. ICCAD Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
1992	A	`conf`	An efficient multi-view design model for real-time interactive synthesis. ICCAD Allen C.-H. Wu, Tedd Hadley, Daniel Gajski
1992	J	`jnl`	Layout placement for sliced architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu
1992	J	`jnl`	Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Allen C.-H. Wu, Daniel D. Gajski
1992	—	`conf`	Timing models for high-level synthesis. EURO-DAC Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski
1992	—	`book`	Youn-Long Steve Lin Daniel D. Gajski, Nikil D. Dutt, Allen C.-H. Wu
1991	—	`conf`	Glue-logic partitioning for floorplans with a rectilinear datapath. EURO-DAC Allen C.-H. Wu, Daniel D. Gajski
1991	A	`conf`	Layout-Area Models for High-Level Synthesis. ICCAD Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski
1990	—	`conf`	A new algorithm for transistor sizing in CMOS circuits. EURO-DAC Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski
1990	A	`conf`	Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD Allen C.-H. Wu, Daniel Gajski