Alireza Mahzoon

32 papers A* 3A 6B 1C 6Journal 7Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Divider verification using symbolic computer algebra and delayed don't care optimization: theory and practical implementation. Formal Methods Syst. Des. Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2025	J	`jnl`	Lower bound proof for the size of BDDs representing a shifted addition. Inf. Process. Lett. Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
2024	J	`jnl`	Polynomial Formal Verification of Arithmetic Circuits. Found. Trends Electron. Des. Autom. Alireza Mahzoon, Rolf Drechsler
2023	A	`conf`	Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. DATE Rolf Drechsler, Alireza Mahzoon
2023	—	`conf`	Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine. Applicable Formal Methods for Safe Industrial Products Alireza Mahzoon, Rolf Drechsler
2023	A	`conf`	Polynomial Formal Verification of Floating Point Adders. DATE Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
2023	—	`conf`	Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
2023	—	`conf`	Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits. ISDCS Rolf Drechsler, Alireza Mahzoon
2022	C	`conf`	ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2022	B	`conf`	Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2022	A*	`conf`	Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
2022	—	`—`	Formal verification of structurally complex multipliers. Alireza Mahzoon
2022	—	`ch.`	Formale Verifikation von strukturell komplexen Multiplizierern. Ausgezeichnete Informatikdissertationen Alireza Mahzoon
2022	J	`jnl`	Lower Bound Proof for the Size of BDDs representing a Shifted Addition. CoRR Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
2022	—	`conf`	Polynomial Formal Verification of Complex Multipliers. MBMV Alireza Mahzoon, Rolf Drechsler
2022	A	`conf`	Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. ICCAD Rolf Drechsler, Alireza Mahzoon
2022	C	`conf`	Preserving Design Hierarchy Information for Polynomial Formal Verification. VLSI-SoC Rolf Drechsler, Alireza Mahzoon
2022	J	`jnl`	RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alireza Mahzoon, Daniel Große, Rolf Drechsler
2022	C	`conf`	Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS Rolf Drechsler, Alireza Mahzoon, Mehran Goli
2021	C	`conf`	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2021	A*	`conf`	Late Breaking Results: Polynomial Formal Verification of Fast Adders. DAC Alireza Mahzoon, Rolf Drechsler
2021	—	`conf`	Polynomial Formal Verification of Prefix Adders. ATS Alireza Mahzoon, Rolf Drechsler
2021	C	`conf`	Polynomial word-level verification of arithmetic circuits. MEMOCODE Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler
2021	A	`conf`	Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2020	C	`conf`	ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. ICCD Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2020	A	`conf`	Towards Formal Verification of Optimized and Industrial Multipliers. DATE Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
2019	A*	`conf`	RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC Alireza Mahzoon, Daniel Große, Rolf Drechsler
2018	—	`conf`	Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI Alireza Mahzoon, Daniel Große, Rolf Drechsler
2018	A	`conf`	PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD Alireza Mahzoon, Daniel Große, Rolf Drechsler
2017	J	`jnl`	OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. IEEE Trans. Very Large Scale Integr. Syst. Alireza Mahzoon, Bijan Alizadeh
2017	J	`jnl`	Systematic Design Space Exploration of Floating-Point Expressions on FPGA. IEEE Trans. Circuits Syst. II Express Briefs Alireza Mahzoon, Bijan Alizadeh
2015	—	`conf`	Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. ISVLSI Alireza Mahzoon, Bijan Alizadeh