Alin Razafindraibe

11 papers C 2Journal 2Unranked 7
YearRankTypeTitle / Venue / Authors
2011 J jnl
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
CoRR
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2008 — conf
Physical Design of FPGA Interconnect to Prevent Information Leakage.
ARC
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2007 — conf
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates.
PATMOS
Alin Razafindraibe, Philippe Maurine
2007 — conf
A Novel Asynchronous e-FPGA Architecture for Security Applications.
FPT
Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
2007 — conf
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.
ReCoSoC
Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
2007 — conf
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.
PATMOS
Alin Razafindraibe, Michel Robert, Philippe Maurine
2007 C conf
Improvement of dual rail logic as a countermeasure against DPA.
VLSI-SoC
Alin Razafindraibe, Michel Robert, Philippe Maurine
2006 — conf
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.
PATMOS
Alin Razafindraibe, Michel Robert, Philippe Maurine
2006 C conf
Security evaluation of dual rail logic against DPA attacks.
VLSI-SoC
Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
2005 — conf
A Method to Design Compact Dual-rail Asynchronous Primitives.
PATMOS
Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
2005 J jnl
Compact and Secured Primitives for the Design of Asynchronous Circuits.
J. Low Power Electron.
Alin Razafindraibe, Michel Robert, Philippe Maurine