Ali Sheikholeslami

102 papers A 3B 1Misc 2Journal 51Unranked 45

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	MOCQA: A Multi-Core Optimizer for Constrained Quadratic Assignment. IEEE Access Mohammad Bagherbeik, Parastoo Ashtari, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2025	J	`jnl`	Sampling via Rejection-Free Partial Neighbor Search. Commun. Stat. Simul. Comput. Sigeng Chen, Jeffrey S. Rosenthal, Aki Dote, Hirotaka Tamura, Ali Sheikholeslami
2024	J	`jnl`	A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI. IEEE Open J. Circuits Syst. Jhoan Salinas, Hossein Shakiba, Ali Sheikholeslami
2024	J	`jnl`	A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers. IEEE Open J. Circuits Syst. Miad Laghaei, Hossein Shakiba, Ali Sheikholeslami
2024	J	`jnl`	A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET Process. IEEE J. Solid State Circuits Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
2024	J	`jnl`	Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication. IEEE Open J. Circuits Syst. Mohammad Emami Meybodi, Hossein Shakiba, Ali Sheikholeslami
2024	J	`jnl`	FBMC vs. PAM and DMT for High-Speed Wireline Communication. IEEE Open J. Circuits Syst. Jeremy Cosson-Martin, Jhoan Salinas, Hossein Shakiba, Ali Sheikholeslami
2024	J	`jnl`	Graph clustering with Boltzmann machines. Discret. Appl. Math. Pierre Miasnikof, Mohammad Bagherbeik, Ali Sheikholeslami
2023	—	`conf`	A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET. VLSI Technology and Circuits Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
2023	—	`conf`	A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process. ESSCIRC Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
2023	J	`jnl`	An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process. IEEE Open J. Circuits Syst. Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
2023	—	`conf`	Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications. MWSCAS Jeremy Cosson-Martin, Miad Laghaei, Hossein Shakiba, Ali Sheikholeslami
2023	J	`jnl`	Optimization via Rejection-Free Partial Neighbor Search. Stat. Comput. Sigeng Chen, Jeffrey S. Rosenthal, Aki Dote, Hirotaka Tamura, Ali Sheikholeslami
2022	J	`jnl`	A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier. IEEE Open J. Circuits Syst. Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
2022	J	`jnl`	An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications. IEEE Open J. Circuits Syst. Jeremy Cosson-Martin, Hossein Shakiba, Ali Sheikholeslami
2022	J	`jnl`	Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE). IEEE Open J. Circuits Syst. Mohammad Emami Meybodi, Hector Gomez, Yu-Chun Lu, Hossein Shakiba, Ali Sheikholeslami
2022	J	`jnl`	Graph clustering with Boltzmann machines. CoRR Pierre Miasnikof, Mohammad Bagherbeik, Ali Sheikholeslami
2022	A	`conf`	MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA. FPGA Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2022	—	`conf`	MAQO: A Scalable Many-Core Annealer for Quadratic Optimization. VLSI Technology and Circuits Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2021	B	`conf`	Caching and Vectorization Schemes to Accelerate Local Search Algorithms for Assignment Problems. CEC Mohammad Bagherbeik, Ali Sheikholeslami
2021	J	`jnl`	Jump Markov chains and rejection-free Metropolis algorithms. Comput. Stat. Jeffrey S. Rosenthal, Aki Dote, Keivan Dabiri, Hirotaka Tamura, Sigeng Chen, Ali Sheikholeslami
2021	J	`jnl`	Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication. IEEE Open J. Circuits Syst. Jhoan Salinas, Jeremy Cosson-Martin, Miad Laghaei, Hossein Shakiba, Ali Sheikholeslami
2021	—	`conf`	The Power of Parallelism in Stochastic Search for Global Optimum: Keynote Paper. ESSCIRC Ali Sheikholeslami
2021	J	`jnl`	Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications. IEEE Open J. Circuits Syst. Jeremy Cosson-Martin, Hossein Shakiba, Ali Sheikholeslami
2020	—	`conf`	A Hamiltonian Engine for Radiotherapy Optimization. EMBC Mehrdad Malekmohammadi, Keivan Dabiri, Joshua Mathews, Daryl Nazareth, Hirotaka Tamura, Ali Sheikholeslami
2020	—	`conf`	A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems. PPSN (1) Mohammad Bagherbeik, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2020	—	`conf`	Keynote II: Digital Annealer: A Stochastic Search for Global Optimum. ISMVL Ali Sheikholeslami
2020	J	`jnl`	Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial. IEEE Trans. Parallel Distributed Syst. Keivan Dabiri, Mehrdad Malekmohammadi, Ali Sheikholeslami, Hirotaka Tamura
2019	—	`conf`	A 30Gb/s 2x Half-Baud-Rate CDR. CICC Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki
2019	—	`conf`	A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS. ISSCC Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki
2019	Misc	`conf`	Digitally Annealed Solution for the Vertex Cover Problem with Application in Cyber Security. ICASSP Mohammad Javad-Kalbasi, Keivan Dabiri, Shahrokh Valaee, Ali Sheikholeslami
2018	J	`jnl`	Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. IEEE J. Solid State Circuits Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2018	J	`jnl`	On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. IEEE J. Solid State Circuits Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2017	—	`conf`	6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. ISSCC Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017	—	`conf`	6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ISSCC Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2017	J	`jnl`	A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. IEEE J. Solid State Circuits Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017	Misc	`conf`	Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. CISIS Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami
2017	—	`conf`	Jitter injection for on-chip jitter measurement in PI-based CDRs. CICC Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2017	—	`conf`	Tutorials. ISSCC Ali Sheikholeslami
2016	A	`conf`	Low-Swing Signaling for FPGA Power Reduction (Abstract Only). FPGA Sayeh Sharifymoghaddam, Ali Sheikholeslami
2015	J	`jnl`	A 3x blind ADC-based CDR for a 20 dB loss channel. IEEE Trans. Circuits Syst. I Regul. Pap. Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015	—	`conf`	A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction. ISMVL Aynaz Vatankhahghadim, Ali Sheikholeslami
2015	J	`jnl`	A Reference-Less Single-Loop Half-Rate Binary CDR. IEEE J. Solid State Circuits Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015	J	`jnl`	A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA. IEEE Trans. Circuits Syst. II Express Briefs Aynaz Vatankhahghadim, W. Song, Ali Sheikholeslami
2015	J	`jnl`	On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. IEEE J. Solid State Circuits Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	—	`conf`	29.2 A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW. ISSCC Yunzhi Dong, Richard Schreier, Wenhua Yang, Sudhir Korrapati, Ali Sheikholeslami
2014	J	`jnl`	A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS. IEEE J. Solid State Circuits Yunzhi Dong, William Yang, Richard Schreier, Ali Sheikholeslami, Sudhir Korrapati
2014	J	`jnl`	A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions. IEEE Trans. Circuits Syst. I Regul. Pap. Aynaz Vatankhahghadim, Safeen Huda, Ali Sheikholeslami
2014	—	`conf`	A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. CICC Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	J	`jnl`	An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". IEEE Trans. Circuits Syst. I Regul. Pap. Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	—	`conf`	On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. VLSIC Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	J	`jnl`	A Blind Baud-Rate ADC-Based CDR. IEEE J. Solid State Circuits Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	J	`jnl`	A Novel STT-MRAM Cell With Disturbance-Free Read Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Safeen Huda, Ali Sheikholeslami
2013	—	`conf`	A blind baud-rate ADC-based CDR. ISSCC Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	—	`conf`	An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. CICC Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	—	`conf`	Design metrics for blind ADC-based wireline receivers. CICC Ali Sheikholeslami, Hirotaka Tamura
2012	—	`conf`	10-40 Gb/s I/O design for data communications. ISSCC Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John T. Stonick, Hisakatsu Yamaguchi
2011	—	`conf`	A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. ISSCC Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	—	`conf`	A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. ISSCC Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	—	`conf`	A pattern-guided adaptive equalizer in 65nm CMOS. ISSCC Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	J	`jnl`	An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS. IEEE J. Solid State Circuits Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	—	`conf`	High-speed transceivers: Standards, challenges, and future. ISSCC Ali Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John T. Stonick, Takuji Yamamoto
2010	J	`jnl`	A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
2010	—	`conf`	A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
2010	—	`conf`	A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. CICC Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune
2010	—	`conf`	A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
2010	—	`conf`	Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. ISSCC David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki
2009	J	`jnl`	A current independent method based on synchronized voltage measurement for fault location on transmission lines. Simul. Model. Pract. Theory Khalil Gorgani Firouzjah, Ali Sheikholeslami
2009	J	`jnl`	A predictive current control method for shunt active filter with windowing based wavelet transform in harmonic detection. Simul. Model. Pract. Theory Khalil Gorgani Firouzjah, Ali Sheikholeslami, Mohammad Reza Karami Mollaei, F. Heydari
2009	—	`conf`	Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial). ISMVL Ali Sheikholeslami
2009	—	`conf`	Will ADCs overtake binary frontends in backplane signaling? ISSCC Ali Sheikholeslami, Robert Payne
2008	J	`jnl`	Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. IEEE Trans. Circuits Syst. I Regul. Pap. Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2008	J	`jnl`	Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM). IEEE J. Solid State Circuits Oleksiy Tyshchenko, Ali Sheikholeslami
2007	J	`jnl`	A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. IEEE J. Solid State Circuits Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2007	J	`jnl`	Low-Power Dual-Microphone Speech Enhancement Using Field Programmable Gate Arrays. IEEE Trans. Signal Process. David Halupka, Alireza Seyed Rabi, Parham Aarabi, Ali Sheikholeslami
2006	—	`conf`	A 3.2Gb/s Semi-Blind-Oversampling CDR. ISSCC Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2006	—	`conf`	A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. CICC Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura
2006	J	`jnl`	An area-efficient universal cryptography processor for smart cards. IEEE Trans. Very Large Scale Integr. Syst. Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Shoichi Masui, Kenji Mukaida
2006	J	`jnl`	Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J. Solid State Circuits Kostas Pagiamtzis, Ali Sheikholeslami
2006	J	`jnl`	Real-time face detection and lip feature extraction using field-programmable gate arrays. IEEE Trans. Syst. Man Cybern. Part B Duy Cuong Nguyen, David Halupka, Parham Aarabi, Ali Sheikholeslami
2005	—	`conf`	Real-time dual-microphone speech enhancement using field programmable gate arrays. ICASSP (5) David Halupka, Alireza Seyed Rabi, Parham Aarabi, Ali Sheikholeslami
2005	J	`jnl`	Robust sound localization in 0.18 µm CMOS. IEEE Trans. Signal Process. David Halupka, Nebu John Mathai, Parham Aarabi, Ali Sheikholeslami
2005	—	`conf`	Using cache to reduce power in content-addressable memories (CAMs). CICC Kostas Pagiamtzis, Ali Sheikholeslami
2004	—	`conf`	A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu
2004	J	`jnl`	A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme. IEEE J. Solid State Circuits Kostas Pagiamtzis, Ali Sheikholeslami
2004	—	`conf`	An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling. SoCC Marcus van Ierssel, Joyce Wong, Ali Sheikholeslami
2004	J	`jnl`	Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). IEEE J. Solid State Circuits Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima
2003	J	`jnl`	A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. IEEE J. Solid State Circuits Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima
2003	J	`jnl`	A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories. IEEE J. Solid State Circuits Igor Arsovski, Ali Sheikholeslami
2003	J	`jnl`	A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. IEEE J. Solid State Circuits Igor Arsovski, Trevis Chandler, Ali Sheikholeslami
2003	J	`jnl`	Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC]. IEEE J. Solid State Circuits Simon Segars, Ali Sheikholeslami, Stephen Fischer
2003	J	`jnl`	Hardware implementation perspectives of digital video watermarking algorithms. IEEE Trans. Signal Process. Nebu John Mathai, Deepa Kundur, Ali Sheikholeslami
2003	J	`jnl`	Introduction: Special Issue in Recognition of Kenneth C. Smith. J. Multiple Valued Log. Soft Comput. Ali Sheikholeslami, D. Michael Miller
2003	—	`conf`	Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories. CICC Kostas Pagiamtzis, Ali Sheikholeslami
2003	—	`conf`	Real-time sound localization using field-programmable gate arrays. ICASSP (2) Duy Cuong Nguyen, Parham Aarabi, Ali Sheikholeslami
2003	A	`conf`	Real-time sound localization using field-programmable gate arrays. ICME Duy Cuong Nguyen, Parham Aarabi, Ali Sheikholeslami
2003	—	`conf`	Signaling capacity of FR4 PCB traces for chip-to-chip communication. ISCAS (5) Marcus van Ierssel, Tooraj Esmailian, Ali Sheikholeslami, P. S. Pasupathy
2003	—	`conf`	VLSI implementation of a real-time video watermark embedder and detector. ISCAS (2) Nebu John Muthui, Ali Sheikholeslami, Deepa Kundur
2002	—	`conf`	A 16 kb 1T1C FeRAM test chip using current-based reference scheme. CICC Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima
2000	J	`jnl`	A survey of circuit innovations in ferroelectric random-access memories. Proc. IEEE Ali Sheikholeslami, P. Glenn Gulak
1998	—	`conf`	Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic. ISMVL Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
1996	—	`conf`	A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu