Ali Jahanian - RankMe

64 papers A 1C 8Misc 2Journal 36Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Efficient Modular Addition for FPGA-Based Cryptographic Operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saeid Gorgin, Amirhossein Sadr, Dara Rahmati, Ali Jahanian, Jungrae Kim
2026	J	`jnl`	Reviewing the interrelationship between FPGA-based dynamic partial reconfiguration technology and vulnerabilities of side-channel analysis attacks. Integr. Ario Kianazad, Milad Salimian, Hamed Hossein-Talaee, Ali Jahanian
2025	J	`jnl`	Protecting the Neural Networks against FGSM Attack Using Machine Unlearning. CoRR Amir Hossein Khorasani, Ali Jahanian, Maryam Rastgarpour
2024	J	`jnl`	Systematic Trojan Detection in Crypto-Systems Using the Model Checker. J. Circuits Syst. Comput. Hamed Hossein-Talaee, Ali Jahanian, Bijan Alizadeh
2023	J	`jnl`	Generic and scalable DNA-based logic design methodology for massive parallel computation. J. Supercomput. Zohre Beiki, Ali Jahanian
2022	J	`jnl`	A Closed-Form Transient Response of Coupled Transmission Lines. IEEE Syst. J. Fatemeh Zahedi, Esfandiar Mehrshahi, Ali Jahanian
2022	J	`jnl`	A Time Randomization-Based Countermeasure Against the Template Side-Channel Attack. ISC Int. J. Inf. Secur. Farshideh Kordi, Hamed Hossein-Talaee, Ali Jahanian
2022	J	`jnl`	Accurate Crosstalk Noise Modeling and Analysis of Non-Identical Lossy Interconnections Using Convex Optimization Method. IEEE Trans. Circuits Syst. I Regul. Pap. Fatemeh Zahedi, Esfandiar Mehrshahi, Ali Jahanian
2022	Misc	`conf`	Flexible and Automatable Microfluidic-based Architecture and CAD Algorithm for Implementation of Large DNA Digital Storage. CSICC Mostafa Pourasadollah, Maryam Taajobian, Ali Jahanian
2022	J	`jnl`	Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process. J. Supercomput. Vahhab Samadi Bokharaie, Ali Jahanian
2021	J	`jnl`	Intensive Analysis of Physical Parameters of Power Sensors for Remote Side-Channel Attacks. ISC Int. J. Inf. Secur. Milad Salimian, Ali Jahanian
2020	J	`jnl`	A Cost & Performance-Efficient Field-Programmable Pin-Constrained Digital Microfluidic Biochip. CoRR Alireza Abdoli, Ali Jahanian
2020	—	`conf`	Analysis of Geometrical Parameters for Remote Side-Channel Attacks on Multi-Tenant FPGAs. ISCISC Milad Salimian, Ali Jahanian
2020	—	`conf`	Cost-Effective and Practical Countermeasure against the Template Side Channel Attack. ISCISC Farshideh Kordi, Hamed Hossein-Talaee, Ali Jahanian
2020	J	`jnl`	Low-Cost Performance-Efficient Field-Programmable Pin-Constrained Digital Microfluidic Biochip. CoRR Alireza Abdoli, Sedigheh Farhadtoosky, Ali Jahanian
2020	—	`conf`	Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault Injection. ISVLSI Mahboube Fakhire, Ali Jahanian
2018	J	`jnl`	Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation. Microprocess. Microsystems Zohre Beiki, Z. Zare Dorabi, Ali Jahanian
2018	—	`conf`	Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management. CCECE Pourya Bayat-Makou, Ali Jahanian, Midia Reshadi
2017	J	`jnl`	Customized Placement Algorithm of Nanoscale DNA Logic Circuits. J. Circuits Syst. Comput. Sedigheh Farhadtoosky, Ali Jahanian
2017	J	`jnl`	DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design. IEEE Trans. Biomed. Circuits Syst. Zohre Mohammadi-Arfa, Ali Jahanian
2017	C	`conf`	High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation. DSD Mercedeh Sanjabi, Ali Jahanian, Maryam Tahmasebi
2017	—	`conf`	Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution. ISVLSI Hamed Hossein-Talaee, Ali Jahanian
2017	—	`conf`	Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers. AsianHOST Sharareh Zamanzadeh, Ali Jahanian
2017	J	`jnl`	Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area. J. Circuits Syst. Comput. Armin Belghadr, Ali Jahanian
2016	J	`jnl`	ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow. ISC Int. J. Inf. Secur. Sharareh Zamanzadeh, Ali Jahanian
2016	J	`jnl`	Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology. Microprocess. Microsystems Sharareh Zamanzadeh, Ali Jahanian
2016	J	`jnl`	Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering. J. Electron. Test. Sharareh Zamanzadeh, Ali Jahanian
2016	—	`conf`	Security improvement of FPGA configuration file against the reverse engineering attack. ISCISC Sharareh Zamanzadeh, Shahram Shahabi, Ali Jahanian
2016	J	`jnl`	Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose. ISC Int. J. Inf. Secur. Sharareh Zamanzadeh, Ali Jahanian
2015	J	`jnl`	A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform. J. Supercomput. H. Daryanavard, Mohammad Eshghi, Ali Jahanian
2015	J	`jnl`	Security-aware register placement to hinder malicious hardware updating and improve Trojan detectability. ISC Int. J. Inf. Secur. Mehrshad Vosoughi, Ali Jahanian
2015	J	`jnl`	Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage. Integr. Marzieh Morshedzadeh, Ali Jahanian, Payam Pourashraf
2014	J	`jnl`	Improved delay and Process variation Tolerant Clock Tree Network in ultra-Large Circuits using Hybrid RF/metal Clock Routing. J. Circuits Syst. Comput. Zohre Mohammadi-Arfa, Ali Jahanian
2014	J	`jnl`	Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs. Integr. Armin Belghadr, Ali Jahanian
2014	J	`jnl`	Trojan Vulnerability Map: An Efficient Metric for Modeling and Improving the Security Level of Hardware. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mahmoud Bakhshizadeh, Ali Jahanian
2013	C	`conf`	Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. VLSI-SoC Sharareh Zamanzadeh, Ali Jahanian
2012	C	`conf`	EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off. DSD Samaneh Talebi, Niloofar Abolghasemi, Ali Jahanian
2012	J	`jnl`	Improved CMOS (4; 2) compressor designs for parallel multipliers. Comput. Electr. Eng. Abdoreza Pishvaie, Ghassem Jaberipur, Ali Jahanian
2012	J	`jnl`	Improved timing closure by analytical buffer and TSV planning in three-dimensional chips. IEICE Electron. Express Reza Abdollahi, Ali Jahanian
2012	—	`conf`	Landmark-based Car Navigation with Overtake Capability in Multi-agent Environments. ICAART (2) Sirvan Khalighi, Somayeh Maabi, Mercedeh Sanjabi, Ali Jahanian
2012	—	`conf`	Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage. ACM Great Lakes Symposium on VLSI Marzieh Morshedzadeh, Ali Jahanian
2012	J	`jnl`	Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects. IEICE Trans. Electron. Mohammad Taghi Teimoori, Ali Jahanian, Adel Dokhanchi
2012	C	`conf`	RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion. DSD Bahareh Pourshirazi, Ali Jahanian
2011	—	`conf`	A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion. ISVLSI Zohre Mohammadi-Arfa, Ali Jahanian
2011	—	`conf`	Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology. ACM Great Lakes Symposium on VLSI Mehdi Alipour, Mohammad Haji Seyed Javadi, Ali Jahanian
2011	—	`conf`	Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage. ISVLSI Adel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi, Mohammad Taghi Teimoori
2011	J	`jnl`	Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. Integr. Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh
2011	J	`jnl`	Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation. IEICE Electron. Express Arash Farkish, Ali Jahanian
2011	C	`conf`	VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. DSD Behzad Salami, Morteza Saheb Zamani, Ali Jahanian
2010	J	`jnl`	Early Buffer Planning with Congestion Control Using Buffer Requirement Map. J. Circuits Syst. Comput. Ali Jahanian, Morteza Saheb Zamani
2009	J	`jnl`	A Landmark-Based Navigation System for High Speed Cars in the Roads with Branches. Int. J. Inf. Acquis. Mercedeh Sanjabi, Somayeh Maabi, Zahra Esmaeili, Ali Jahanian, Sirvan Khalighi
2009	—	`conf`	Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI Ali Jahanian, Morteza Saheb Zamani
2009	A	`conf`	Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. DATE Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani
2008	Misc	`conf`	Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. CSICC Ali Jahanian, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi
2008	—	`conf`	Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani
2008	C	`conf`	Performance and Timing Yield Enhancement using Highway-on-Chip Planning. DSD Ali Jahanian, Morteza Saheb Zamani
2008	J	`jnl`	Using metro-on-chip in physical design flow for congestion and routability improvement. Microelectron. J. Ali Jahanian, Morteza Saheb Zamani
2007	J	`jnl`	Evaluation, prediction and reduction of routing congestion. Microelectron. J. Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
2007	—	`conf`	Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI Ali Jahanian, Morteza Saheb Zamani
2007	J	`jnl`	Metro-on-chip: an efficient physical design technique for congestion reduction. IEICE Electron. Express Ali Jahanian, Morteza Saheb Zamani
2006	—	`conf`	Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. ISVLSI Ali Jahanian, Morteza Saheb Zamani
2006	—	`conf`	Prediction and reduction of routing congestion. ISPD Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
2005	C	`conf`	Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. DSD Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari
2004	C	`conf`	Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. DSD Mohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi