Alexey Lopich

14 papers C 7Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2014 C conf
Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision.
ISCAS
Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
2013 — conf
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array.
CICC
Alexey Lopich, Piotr Dudek
2012 — conf
Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps.
ICECS
Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
2011 J jnl
A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alexey Lopich, Piotr Dudek
2011 C conf
A processor element for a mixed signal cellular processor array vision chip.
ISCAS
Stephen J. Carey, Alexey Lopich, Piotr Dudek
2011 C conf
Architecture and design of a programmable 3D-integrated cellular processor array for image processing.
VLSI-SoC
Alexey Lopich, Piotr Dudek
2011 J jnl
Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array.
Int. J. Circuit Theory Appl.
Alexey Lopich, Piotr Dudek
2011 C conf
Live demonstration: Real-time image processing on ASPA2 vision system.
ISCAS
Alexey Lopich, David Robert Wallace Barr, Bin Wang, Piotr Dudek
2010 C conf
An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology.
ISCAS
Alexey Lopich, Piotr Dudek
2009 — conf
A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology.
ECCTD
Piotr Dudek, Alexey Lopich, Viktor Gruev
2009 J jnl
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing.
J. Signal Process. Syst.
Alexey Lopich, Piotr Dudek
2008 C conf
ASPA: Focal Plane digital processor array with asynchronous processing capabilities.
ISCAS
Alexey Lopich, Piotr Dudek
2007 — conf
Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array.
ECCTD
Alexey Lopich, Piotr Dudek
2006 C conf
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing.
ISCAS
Alexey Lopich, Piotr Dudek