Alexandru Tanase

26 papers C 2Journal 8Unranked 15

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2018	—	`conf`	Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
2018	J	`jnl`	Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2017	J	`jnl`	A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal
2017	—	`conf`	A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2017	—	`conf`	Efficiency in ILP processing by using orthogonality. ASAP Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
2017	—	`conf`	Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
2017	—	`—`	Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme. Alexandru Tanase
2017	—	`conf`	TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich
2016	—	`conf`	Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
2016	J	`jnl`	Providing fault tolerance through invasive computing. it Inf. Technol. Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
2015	—	`conf`	A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
2015	—	`conf`	Adaptive fault tolerance through invasive computing. AHS Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting
2015	—	`conf`	On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
2015	C	`conf`	Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2015	J	`jnl`	Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
2014	—	`conf`	Domain-specific augmentations for High-Level Synthesis. ASAP Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal
2014	J	`jnl`	Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche
2014	J	`jnl`	Massively Parallel Processor Architectures for Resource-aware Computing. CoRR Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. Jürgen Teich, Alexandru Tanase, Frank Hannig
2014	C	`conf`	Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2013	—	`conf`	A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2013	—	`conf`	Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2013	—	`conf`	Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich
2013	—	`conf`	High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO Moritz Schmid, Frank Hannig, Alexandru Tanase, Jürgen Teich
2013	—	`conf`	Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP Jürgen Teich, Alexandru Tanase, Frank Hannig