Alexandru Amaricai

47 papers B 2C 12Misc 5Journal 6Unranked 22

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Iterative Gradient Descent Decoding for Real Number LDPC Codes. CoRR Oana Boncalo, Alexandru Amaricai
2023	—	`conf`	Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes. DFT Oana Boncalo, Alexandru Amaricai
2020	Misc	`conf`	Layered LDPC decoder in-order message access scheduling: a case study. SACI Oana Boncalo, Alexandru Amaricai
2019	—	`conf`	A Log-Likelihood Ratio based Generalized Belief Propagation. EUROCON Alexandru Amaricai, Mohsen Bahrami, Bane Vasic
2019	C	`conf`	Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller. DSD Oana Boncalo, Alexandru Amaricai, Zsófia Lendek
2019	J	`jnl`	Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation. IEEE Trans. Circuits Syst. I Regul. Pap. Oana Boncalo, Gyorgy Kolumban-Antal, Alexandru Amaricai, Valentin Savin, David Declercq
2018	C	`conf`	Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding. DSD Oana Boncalo, Alexandru Amaricai, Sergiu Nimara
2017	J	`jnl`	On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers. J. Circuits Syst. Comput. Alexandru Amaricai, Ovidiu Sicoe, Oana Boncalo
2017	—	`conf`	Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders. ISVLSI Oana Boncalo, Alexandru Amaricai
2017	—	`conf`	Unrolled layered architectures for non-surjective finite alphabet iterative decoders. NORCAS Oana Boncalo, Valentin Savin, Alexandru Amaricai
2016	—	`conf`	Configurable FPGA architecture for hardware-software merge sorting. MIXDES Patricia Carla Petrut, Alexandru Amaricai, Oana Boncalo
2016	C	`conf`	FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization. DDECS Sergiu Nimara, Oana Boncalo, Alexandru Amaricai, Mircea Popa
2016	—	`conf`	Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting. ARCS Marius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu
2016	—	`conf`	Reliability analysis of memory centric LDPC decoders under probabilistic storage failures. ICECS Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Emanuel M. Popovici
2016	—	`conf`	Variable throughput LDPC decoders using SIMD-based adaptive quantization. TSP Virgil E. Petcu, Oana Boncalo, Alexandru Amaricai, Valentin Savin
2015	—	`conf`	Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders. MIXDES Andrei Hera, Oana Boncalo, Constantina-Elena Gavriliu, Alexandru Amaricai, Valentin Savin, David Declercq, Fakhreddine Ghaffari
2015	—	`conf`	Direct FPGA-based power profiling for a RISC processor. I2MTC Cosmin Cernazanu-Glavan, Marius Marcu, Alexandru Amaricai, Stefan Fedeac, Madalin Ghenea, Zheng Wang, Anupam Chattopadhyay, Jan Weinstock, Rainer Leupers
2015	—	`conf`	FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding. NEWCAS Truong Nguyen-Ly, Khoa Le, Fakhreddine Ghaffari, Alexandru Amaricai, Oana Boncalo, Valentin Savin, David Declercq
2015	Misc	`conf`	Generation of floating point 2D translation operators for FPGA. SACI Ovidiu Sicoe, Alexandru Amaricai, Mircea Popa
2015	C	`conf`	Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques. DDECS Ioana Mot, Oana Boncalo, Alexandru Amaricai
2015	Misc	`conf`	Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands. SACI Sergiu Nimara, Alexandru Amaricai, Mircea Popa
2015	C	`conf`	Template-based QC-LDPC decoder architecture generation. ICICS Oana Boncalo, Petru Florin Mihancea, Alexandru Amaricai
2014	B	`conf`	An FPGA sliding window-based architecture harris corner detector. FPL Alexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo
2014	—	`conf`	Cost effective FPGA probabilistic fault emulation. NORCHIP Oana Boncalo, Alexandru Amaricai, Christian Spagnol, Emanuel M. Popovici
2014	B	`conf`	Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing. FPL Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin
2014	—	`conf`	Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits. ISVLSI Jiaoyan Chen, Christian Spagnol, Satish Grandhi, Emanuel M. Popovici, Sorin Cotofana, Alexandru Amaricai
2014	J	`jnl`	Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays. IET Comput. Digit. Tech. Alexandru Amaricai, Oana Boncalo, Constantina-Elena Gavriliu
2014	—	`conf`	Memory efficient implementation of self-corrected min-sum LDPC decoder. ICECS Oana Boncalo, Alexandru Amaricai, Valentin Savin
2014	C	`conf`	Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits. DSD Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici
2013	—	`conf`	FPGA implementation of hybrid fixed point - Floating point multiplication. MIXDES Alexandru Amaricai, Oana Boncalo, Ovidiu Sicoe, Marius Marcu
2013	—	`conf`	SRT radix-2 dividers with (5, 4) redundant representation of partial remainder. NORCHIP Alexandru Amaricai, Oana Boncalo
2012	—	`conf`	A cycle-count-accurate simulation platform with enhanced design exploration capability. SimuTools Oana Boncalo, Alin Dobre, Alexandru Amaricai, Andrei V. Tanase
2012	—	`conf`	Automatic Generation of FPGA Hardware Accelerators for Graphics Applications. PECCS Alexandru Amaricai, Oana Boncalo
2012	—	`conf`	FPGA implementation of very high radix square root with prescaling. ICECS Alexandru Amaricai, Oana Boncalo
2011	Misc	`conf`	Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator. SACI Alexandru Amaricai, Alin Dobre, Oana Boncalo, Andrei V. Tanase, Camelia Valuch
2010	J	`jnl`	Design Issues and Implementations for Floating-Point Divide-Add Fused. IEEE Trans. Circuits Syst. II Express Briefs Alexandru Amaricai, Mircea Vladutiu, Oana Boncalo
2010	J	`jnl`	Quantum circuit's reliability assessment with VHDL-based simulated fault injection. Microelectron. Reliab. Oana Boncalo, Alexandru Amaricai, Mihai Udrescu, Mircea Vladutiu
2009	C	`conf`	Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation. DSD Alexandru Amaricai, Oana Boncalo
2009	C	`conf`	Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation. DSD Oana Boncalo, Alexandru Amaricai
2008	C	`conf`	A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. DDECS Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu
2008	—	`conf`	Floating point multiplication rounding schemes for interval arithmetic. ASAP Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo
2007	—	`conf`	Assessing quantum circuits reliability with mutant-based simulated fault injection. ECCTD Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
2007	C	`conf`	Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. DDECS Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
2007	C	`conf`	Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. DSD Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
2007	C	`conf`	Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. DSD Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
2007	Misc	`conf`	Simulated Fault Injection for Quantum Circuits Based on Simulator Commands. SACI Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
2007	—	`conf`	Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits. Annual Simulation Symposium Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai