Alexandre Valentian

48 papers A* 1A 2B 2C 3Misc 2Journal 16Unranked 22
YearRankTypeTitle / Venue / Authors
2024 — conf
A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS.
APCCAS
Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian
2024 J jnl
Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey.
IEEE Trans. Neural Networks Learn. Syst.
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2024 — conf
Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS.
APCCAS
Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian
2023 J jnl
Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study.
IEEE Trans. Emerg. Top. Comput. Intell.
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2023 B conf
Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses.
IJCNN
Manon Dampfhoffer, Joel Minguet Lopez, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2023 Misc conf
Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting.
ICASSP
Manon Dampfhoffer, Thomas Mesquida, Emmanuel Hardy, Alexandre Valentian, Lorena Anghel
2023 J jnl
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration.
CoRR
Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy
2023 J jnl
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration.
IEEE J. Solid State Circuits
Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy
2022 J jnl
2022 roadmap on neuromorphic computing and engineering.
Neuromorph. Comput. Eng.
Dennis V. Christensen, Regina Dittmann, Bernabé Linares-Barranco, Abu Sebastian, Manuel Le Gallo, Andrea Redaelli, Stefan Slesazeck, Thomas Mikolajick, Sabina Spiga, Stephan Menzel, Ilia Valov, Gianluca Milano, Carlo Ricciardi, Shi-Jun Liang, Feng Miao, Mario Lanza, Tyler J. Quill, Scott T. Keene, Alberto Salleo, Julie Grollier, Danijela Markovic, Alice Mizrahi, Peng Yao, J. Joshua Yang, Giacomo Indiveri, John Paul Strachan, Suman Datta, Elisa Vianello, Alexandre Valentian, Johannes Feldmann, Xuan Li, Wolfram H. P. Pernice, Harish Bhaskaran, Steve B. Furber, Emre Neftci, Franz Scherr, Wolfgang Maass, Srikanth Ramaswamy, Jonathan Tapson, Priyadarshini Panda, Youngeun Kim, Gouhei Tanaka, Simon Thorpe, Chiara Bartolozzi, Thomas A. Cleland, Christoph Posch, Shih-Chii Liu, Gabriella Panuccio, Mufti Mahmud, Arnab Neelim Mazumder, Morteza Hosseini, Tinoosh Mohsenin, Elisa Donati, Silvia Tolu, Roberto Galeazzi, Martin Ejsing Christensen, Sune Holm, Daniele Ielmini, Nini Pryds
2022 — conf
Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks.
ICANN (3)
Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel
2021 J jnl
2021 Roadmap on Neuromorphic Computing and Engineering.
CoRR
Dennis V. Christensen, Regina Dittmann, Bernabé Linares-Barranco, Abu Sebastian, Manuel Le Gallo, Andrea Redaelli, Stefan Slesazeck, Thomas Mikolajick, Sabina Spiga, Stephan Menzel, Ilia Valov, Gianluca Milano, Carlo Ricciardi, Shi-Jun Liang, Feng Miao, Mario Lanza, Tyler J. Quill, Scott T. Keene, Alberto Salleo, Julie Grollier, Danijela Markovic, Alice Mizrahi, Peng Yao, J. Joshua Yang, Giacomo Indiveri, John Paul Strachan, Suman Datta, Elisa Vianello, Alexandre Valentian, Johannes Feldmann, Xuan Li, Wolfram H. P. Pernice, Harish Bhaskaran, Emre Neftci, Srikanth Ramaswamy, Jonathan Tapson, Franz Scherr, Wolfgang Maass, Priyadarshini Panda, Youngeun Kim, Gouhei Tanaka, Simon Thorpe, Chiara Bartolozzi, Thomas A. Cleland, Christoph Posch, Shih-Chii Liu, Arnab Neelim Mazumder, Morteza Hosseini, Tinoosh Mohsenin, Elisa Donati, Silvia Tolu, Roberto Galeazzi, Martin Ejsing Christensen, Sune Holm, Daniele Ielmini, Nini Pryds
2021 — conf
Overcoming the Data Deluge Challenges with Greener Electronics.
ESSCIRC
Jean-René Léquepeys, Marc Duranton, Susana Bonnetier, Sandrine Catrou, Richard Fournel, Thomas Ernst, Laurent Hérault, D. Louis, A. Jerraya, Alexandre Valentian, François Perruchot, Thomas Signamarcheix, Elisa Vianello, Carlo Reita
2021 — conf
Overcoming the Data Deluge Challenges with Greener Electronics.
ESSDERC
Jean-René Léquepeys, Marc Duranton, Susana Bonnetier, Sandrine Catrou, Richard Fournel, Thomas Ernst, Laurent Hérault, D. Louis, A. Jerraya, Alexandre Valentian, François Perruchot, Thomas Signamarcheix, Elisa Vianello, Carlo Reita
2021 A* conf
Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers.
DAC
Maxence Bouvier, Alexandre Valentian, Gilles Sicard
2020 — conf
Fully-Integrated Spiking Neural Network Using SiOx-Based RRAM as Synaptic Device.
AICAS
Amir Regev, Alessandro Bricalli, Giuseppe Piccolboni, Alexandre Valentian, Thomas Mesquida, Gabriel Molas, Jean-François Nodin
2020 — conf
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
VLSI Circuits
Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Anthony Quelen, Emmanuel Pluchart, Jean-Philippe Noel, Reda Boumchedda, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Alexandre Valentian, Frédéric Heitzmann, Edith Beigné, Fabien Clermidy
2020 J jnl
Spiking Neural Networks Hardware Implementations and Challenges: a Survey.
CoRR
Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné
2019 A conf
Advanced 3D Technologies and Architectures for 3D Smart Image Sensors.
DATE
Pascal Vivet, Gilles Sicard, Laurent Millet, Stéphane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sébastien Thuries, Didier Lattard, Séverine Cheramy, Perrine Batude, Fabien Clermidy
2019 J jnl
Spiking Neural Networks Hardware Implementations and Challenges: A Survey.
ACM J. Emerg. Technol. Comput. Syst.
Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné
2018 — conf
Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks.
ICECS
Elisa Vianello, Denys R. B. Ly, Selina La Barbera, Thomas Dalgaty, Niccolo Castellani, Gabriele Navarro, Guillaume Bourgeois, Alexandre Valentian, Etienne Nowak, Damien Querlioz
2017 — conf
Architecture exploration of a fixed point computation unit using precise timing spiking neurons.
PATMOS
Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
2016 — conf
From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose.
3DIC
Gerald Cibrario, Nour Ben Salem, Joris Lacord, Karim Azizi-Mourier, Olivier Rozeau, Etienne Maurin, Olivier Billoint, Sébastien Thuries, Alexandre Valentian
2016 J jnl
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.
Microelectron. J.
Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol
2015 J jnl
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits
Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015 J jnl
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet
2015 C conf
Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.
RC
Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet
2015 — conf
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.
ESSDERC
Edith Beigné, Jean-Frédéric Christmann, Alexandre Valentian, Olivier Billoint, Esteve Amat, Dominique Morche
2014 — conf
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.
ISSCC
Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2014 J jnl
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.
J. Low Power Electron.
Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville
2014 — conf
Advanced technologies for brain-inspired computing.
ASP-DAC
Fabien Clermidy, Rodolphe Héliot, Alexandre Valentian, Christian Gamrat, Olivier Bichler, Marc Duranton, Bilel Belhadj, Olivier Temam
2014 — conf
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.
PATMOS
Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol
2014 B conf
Shadow-scan design with low latency overhead and in-situ slack-time monitoring.
ETS
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman
2014 Misc conf
The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators.
CASES
Bilel Belhadj, Alexandre Valentian, Pascal Vivet, Marc Duranton, Liqiang He, Olivier Temam
2013 — conf
An efficient metric of setup time for pulsed flip-flops based on output transition time.
ICICDT
Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat
2013 C conf
Comparing CMOS-Based and NEMS-Based Adiabatic Logic Circuits.
RC
Samer Houri, Alexandre Valentian, Hervé Fanet
2013 C conf
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.
VLSI-SoC
Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné
2013 A conf
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.
DATE
Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
2012 — conf
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing.
ICICDT
Dimitri Soussan, Alexandre Valentian, Sylvain Majcherczak, Marc Belleville
2012 — conf
Design challenges for nano-scale devices.
ESSDERC
Marc Belleville, Olivier Thomas, Alexandre Valentian, Fabien Clermidy
2011 — conf
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
ISSCC
Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard
2009 J jnl
An Asynchronous Power Aware and Adaptive NoC Based Circuit.
IEEE J. Solid State Circuits
Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton
2009 — conf
Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits.
3DIC
Lionel Cadix, Alexis Farcy, Cédric Bermond, Christine Fuchs, Patrick Leduc, Maxime Rousseau, Myriam Assous, Alexandre Valentian, Julie Roullard, Elie Eid, Nicolas Sillon, Bernard Fléchet, Pascal Ancey
2009 J jnl
Power Reduction of Asynchronous Logic Circuits Using Activity Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008 — conf
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.
ESSCIRC
Edith Beigné, Fabien Clermidy, Sylvain Miermont, Alexandre Valentian, Pascal Vivet, S. Barasinski, F. Blisson, N. Kohli, S. Kumar
2008 J jnl
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability.
IEEE J. Solid State Circuits
Alexandre Valentian, Edith Beigné
2008 — conf
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.
ASYNC
Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2007 — conf
Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction.
ESSCIRC
Alexandre Valentian, Edith Beigné
2004 J jnl
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara