Alexandre Levisse

48 papers A* 2A 2C 3Misc 1Journal 21Unranked 19

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	HEEPidermis: A Versatile SoC for BioZ Recording. LASCAS Juan Sapriza, Beatrice Grassano, Alessio Naclerio, Filippo Quadri, Tommaso Terzano, David Mallasén, Pasquale Davide Schiavone, Robin Leplae, Jérémie Moullet, Alexandre Levisse, Christoph Müller, Mariagrazia Graziano, Matías R. Miguez, David Atienza
2025	J	`jnl`	HEEPidermis: a versatile SoC for BioZ recording. CoRR Juan Sapriza, Beatrice Grassano, Alessio Naclerio, Filippo Quadri, Tommaso Terzano, David Mallasén, Pasquale Davide Schiavone, Robin Leplae, Jérémie Moullet, Alexandre Levisse, Christoph Müller, Mariagrazia Graziano, Matías R. Miguez, David Atienza
2025	J	`jnl`	Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. IEEE Trans. Emerg. Top. Comput. Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza
2025	J	`jnl`	SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation. ACM Trans. Embed. Comput. Syst. Rafael Medina Morillas, Pengbo Yu, Alexandre Levisse, Dwaipayan Biswas, Marina Zapater, Giovanni Ansaloni, Francky Catthoor, David Atienza
2024	J	`jnl`	An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. IEEE Trans. Very Large Scale Integr. Syst. Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
2024	J	`jnl`	Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rafael Medina, Giovanni Ansaloni, Marina Zapater, Alexandre Levisse, Saeideh Alinezhad Chamazcoti, Timon Evenblij, Dwaipayan Biswas, Francky Catthoor, David Atienza
2024	—	`conf`	DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD. ISVLSI Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
2024	J	`jnl`	Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza
2023	J	`jnl`	ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. IEEE Trans. Computers Joshua Alexander Harrison Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
2023	J	`jnl`	An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors. IEEE J. Emerg. Sel. Topics Circuits Syst. Silvio Zanoli, Flavio Ponzina, Tomás Teijeiro, Alexandre Levisse, David Atienza
2023	J	`jnl`	Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2023	J	`jnl`	Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors. IEEE Wirel. Commun. Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Joshua Alexander Harrison Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
2023	J	`jnl`	Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2023	J	`jnl`	Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Miroslav Vasic, David Atienza
2022	J	`jnl`	A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza
2022	J	`jnl`	A Soft SIMD Based Energy Efficient Computing Microarchitecture. CoRR Pengbo Yu, Alexandre Levisse, Mohit Gupta, Timon Evenblij, Giovanni Ansaloni, Francky Catthoor, David Atienza
2022	J	`jnl`	ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning. CoRR Joshua Alexander Harrison Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
2022	J	`jnl`	Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2022	—	`conf`	Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2022	—	`conf`	Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. ACM Great Lakes Symposium on VLSI Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
2021	—	`conf`	A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2021	—	`conf`	Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF Joshua Alexander Harrison Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal
2021	A*	`conf`	Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
2021	A	`conf`	Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2020	C	`conf`	A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. VLSI-SOC William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
2020	J	`jnl`	Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors. IEEE Trans. Very Large Scale Integr. Syst. Loris Duch, Miguel Peón-Quirós, Pieter Weckx, Alexandre Levisse, Rubén Braojos, Francky Catthoor, David Atienza
2020	J	`jnl`	BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
2020	—	`conf`	Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters. ISVLSI Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza
2020	Misc	`conf`	Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. ICASSP Alexandre Levisse, Marco Rios, Miguel Peón-Quirós, David Atienza
2020	J	`jnl`	Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors. CoRR Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed Elsayed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Joshua Alexander Harrison Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
2020	—	`conf`	RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. ASP-DAC Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza
2020	—	`conf`	Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology. ACM Great Lakes Symposium on VLSI Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza
2020	J	`jnl`	Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
2019	A	`conf`	A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays. ISLPED Halima Najibi, Alexandre Levisse, Marina Zapater
2019	A*	`conf`	A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture. DAC William Andrew Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza
2019	C	`conf`	An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
2019	—	`conf`	BLADE: A BitLine Accelerator for Devices on the Edge. ACM Great Lakes Symposium on VLSI William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza
2019	—	`conf`	Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza
2019	—	`conf`	RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
2019	J	`jnl`	Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays. IEEE Trans. Circuits Syst. II Express Briefs Mouhamad Alayan, Eloi Muhr, Alexandre Levisse, Marc Bocquet, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, Jean-Michel Portal
2018	—	`conf`	RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2018	—	`conf`	Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications. IRPS Gilbert Sassine, Cecile Nail, Luc Tillie, Diego Alfaro Robayo, Alexandre Levisse, Carlo Cagli, Khalil El Hajjam, Jean-Francois Nodin, Elisa Vianello, Mathieu Bernard, Gabriel Molas, Etienne Nowak
2017	—	`conf`	Architecture, design and technology guidelines for crosspoint memories. NANOARCH Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2017	C	`conf`	Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon
2017	—	`conf`	High density emerging resistive memories: What are the limits? LASCAS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2016	—	`conf`	Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal
2015	—	`conf`	SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2014	—	`conf`	Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination. LATW S. Ben Krit, Wenceslas Rahajandraibe, Karine Castellani-Coulié, Gilles Micolau, Alexandre Levisse, A. Lyoussi