Alexander Zaslavsky

15 papers A* 2A 2Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
Optimization of Discrete Parameters Using the Adaptive Gradient Method and Directed Evolution.
CoRR
Andrei Beinarovich, Sergey Stepanov, Alexander Zaslavsky
2018 J jnl
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
2016 A* conf
A fast simulator for the analysis of sub-threshold thermal noise transients.
DAC
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
2016 — conf
Design of Error-Resilient Logic Gates with Reinforcement Using Implications.
ACM Great Lakes Symposium on VLSI
Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson
2015 — conf
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits.
ACM Great Lakes Symposium on VLSI
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
2012 — conf
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.
ACM Great Lakes Symposium on VLSI
Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy
2012 — conf
Z
ESSDERC
Jing Wan, Cyrille Le Royer, Alexander Zaslavsky, Sorin Cristoloveanu
2010 — conf
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.
ACM Great Lakes Symposium on VLSI
Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007 J jnl
Designing Nanoscale Logic Circuits Based on Markov Random Fields.
J. Electron. Test.
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007 A conf
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.
DATE
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007 — conf
Thermally-induced soft errors in nanoscale CMOS circuits.
NANOARCH
Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar
2006 A conf
Designing MRF based error correcting circuits for memory elements.
DATE
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 J jnl
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.
IEEE Micro
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 — conf
Optimizing noise-immune nanoscale circuits using principles of Markov random fields.
ACM Great Lakes Symposium on VLSI
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2005 A* conf
Designing logic circuits for probabilistic computation in the presence of noise.
DAC
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky