Alexander V. Veidenbaum

162 papers A* 11A 24B 11C 10Misc 8Journal 38Unranked 56

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Eliminating Multi-GPU Performance Taxes: A Systems Approach to Efficient Distributed LLMs. CoRR Octavian Alexandru Trifan, Karthik Sangaiah, Muhammad Awad, Muhammad Osama, Sumanth Gudaparthi, Alexandru Nicolau, Alexander V. Veidenbaum, Ganesh Dasika
2025	A*	`conf`	Grammar Pruning: Enabling Low-Latency Zero-Shot Task-Oriented Language Models for Edge AI. EMNLP Octavian Alexandru Trifan, Jason Lee Weber, Marc Titus Trifan, Alexandru Nicolau, Alexander V. Veidenbaum
2024	J	`jnl`	Hyperdimensional computing: a framework for stochastic computation and symbolic AI. J. Big Data Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2023	—	`conf`	A Multiple Compiler Framework for Improved Performance. LCPC Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum
2023	A*	`conf`	DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication. KDD Igor Nunes, Mike Heddes, Pere Vergés, Danny Abraham, Alexander V. Veidenbaum, Alex Nicolau, Tony Givargis
2023	J	`jnl`	DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication. CoRR Igor Nunes, Mike Heddes, Pere Vergés, Danny Abraham, Alexander V. Veidenbaum, Alexandru Nicolau, Tony Givargis
2023	—	`conf`	Enhancing the Privacy of Machine Learning via faster arithmetic over Torus FHE. CSCloud/EdgeCom Marc Titus Trifan, Alexandru Nicolau, Alexander V. Veidenbaum
2023	J	`jnl`	Enhancing the Privacy of Machine Learning via faster arithmetic over Torus FHE. IACR Cryptol. ePrint Arch. Marc Titus Trifan, Alexandru Nicolau, Alexander V. Veidenbaum
2023	J	`jnl`	Torchhd: An Open Source Python Library to Support Research on Hyperdimensional Computing and Vector Symbolic Architectures. J. Mach. Learn. Res. Mike Heddes, Igor Nunes, Pere Vergés, Denis Kleyko, Danny Abraham, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2023	—	`conf`	Using Hyperdimensional Computing to Extract Features for the Detection of Type 2 Diabetes. IPDPS Workshops Neftali Watkinson, Divya Devineni, Victor Joe, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2022	—	`conf`	A Heterogeneous Solution to the All-pairs Shortest Path Problem using FPGAs. ISQED Mihnea Chirila, Paolo D'Alberto, Hsin-Yu Ting, Alexander V. Veidenbaum, Alexandru Nicolau
2022	A	`conf`	GraphHD: Efficient graph classification using hyperdimensional computing. DATE Igor Nunes, Mike Heddes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2022	J	`jnl`	GraphHD: Efficient graph classification using hyperdimensional computing. CoRR Igor Nunes, Mike Heddes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2022	J	`jnl`	Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table. CoRR Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2022	A*	`conf`	Hyperdimensional hashing: a robust and efficient dynamic hash table. DAC Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum
2021	—	`conf`	Class-Modeling of Septic Shock With Hyperdimensional Computing. EMBC Neftali Watkinson, Tony Givargis, Victor Joe, Alexandru Nicolau, Alexander V. Veidenbaum
2021	—	`conf`	Detecting COVID-19 Related Pneumonia On CT Scans Using Hyperdimensional Computing. EMBC Neftali Watkinson, Tony Givargis, Victor Joe, Alexandru Nicolau, Alexander V. Veidenbaum
2020	—	`conf`	NumbaSummarizer: A Python Library for Simplified Vectorization Reports. IPDPS Workshops Neftali Watkinson, Preston Tai, Alexandru Nicolau, Alexander V. Veidenbaum
2019	A	`conf`	AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms. FPGA Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau
2019	A	`conf`	Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance. IPDPS Gongjin Sun, Junjie Shen, Alexander V. Veidenbaum
2019	J	`jnl`	MCompiler: A Synergistic Compilation Framework. CoRR Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum
2019	—	`conf`	Teaching Parallel Computing and Dependence Analysis with Python. IPDPS Workshops Neftali Watkinson, Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum
2019	J	`jnl`	Towards an Achievable Performance for the Loop Nests. CoRR Aniket Shivam, Neftali Watkinson, Alexandru Nicolau, David A. Padua, Alexander V. Veidenbaum
2018	Misc	`conf`	Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines. FCCM Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau
2018	J	`jnl`	An empirical study of the effect of source-level loop transformations on compiler stability. Proc. ACM Program. Lang. Zhangxiaowen Gong, Zhi Chen, Justin Josef Szaday, David C. Wong, Zehra Sura, Neftali Watkinson, Saeed Maleki, David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, Josep Torrellas
2018	—	`conf`	New Opportunities for Compilers in Computer Security. LCPC Junjie Shen, Zhi Chen, Nahid Farhady Ghalaty, Rosario Cammarota, Alexandru Nicolau, Alexander V. Veidenbaum
2018	A	`conf`	OpenCV.js: computer vision processing for the open web platform. MMSys Sajjad Taheri, Alexander V. Veidenbaum, Alexandru Nicolau, Ningxin Hu, Mohammad R. Haghighat
2018	—	`conf`	Towards an Achievable Performance for the Loop Nests. LCPC Aniket Shivam, Neftali Watkinson, Alexandru Nicolau, David A. Padua, Alexander V. Veidenbaum
2017	C	`conf`	CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization. FDTC Zhi Chen, Junjie Shen, Alex Nicolau, Alexander V. Veidenbaum, Nahid Farhady Ghalaty, Rosario Cammarota
2017	J	`jnl`	CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization. IACR Cryptol. ePrint Arch. Zhi Chen, Junjie Shen, Alex Nicolau, Alexander V. Veidenbaum, Nahid Farhady Ghalaty, Rosario Cammarota
2017	—	`conf`	LORE: A loop repository for the evaluation of compilers. IISWC Zhi Chen, Zhangxiaowen Gong, Justin Josef Szaday, David C. Wong, David A. Padua, Alexandru Nicolau, Alexander V. Veidenbaum, Neftali Watkinson, Zehra Sura, Saeed Maleki, Josep Torrellas, Gerald DeJong
2017	J	`jnl`	Special issue on energy efficient multi-core and many-core systems, Part II. J. Parallel Distributed Comput. Amir-Mohammad Rahmani, Pasi Liljeberg, José Luis Ayala, Hannu Tenhunen, Alexander V. Veidenbaum
2017	—	`conf`	Using Hardware Counters to Predict Vectorization. LCPC Neftali Watkinson, Aniket Shivam, Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, Zhangxiaowen Gong
2016	—	`conf`	Data-rate-aware FPGA-based acceleration framework for streaming applications. ReConFig Siavash Rezaei, César-Alejandro Hernández-Calderón, Saeed Mirzamohammadi, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alex Nicolau, Michael J. Prather
2016	—	`conf`	Polygonal Iteration Space Partitioning. LCPC Aniket Shivam, Alexandru Nicolau, Alexander V. Veidenbaum, Mario Mango Furnari, Rosario Cammarota
2016	—	`conf`	SIMD-based soft error detection. Conf. Computing Frontiers Zhi Chen, Alexandru Nicolau, Alexander V. Veidenbaum
2016	J	`jnl`	Special issue on energy efficient multi-core and many-core systems, Part I. J. Parallel Distributed Comput. Amir-Mohammad Rahmani, Pasi Liljeberg, José Luis Ayala, Hannu Tenhunen, Alexander V. Veidenbaum
2015	—	`conf`	Software fault tolerance for FPUs via vectorization. SAMOS Zhi Chen, Ryoichi Inagaki, Alexandru Nicolau, Alexander V. Veidenbaum
2015	—	`conf`	WebRTCbench: a benchmark for performance assessment of webRTC implementations. ESTIMedia Sajjad Taheri, Laleh Aghababaie Beni, Alexander V. Veidenbaum, Alexandru Nicolau, Rosario Cammarota, Jianlin Qiu, Qiang Lu, Mohammad R. Haghighat
2014	C	`conf`	A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms. NPC Yizhuo Wang, Laleh Aghababaie Beni, Alexandru Nicolau, Alexander V. Veidenbaum, Rosario Cammarota
2014	—	`conf`	Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies. ICS 25th Anniversary Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum
2014	—	`conf`	Dynamic-vector execution on a general purpose EDGE chip multiprocessor. ICSAMOS Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum
2014	—	`conf`	Multiple stream tracker: a new hardware stride prefetcher. Conf. Computing Frontiers Taesu Kim, Dali Zhao, Alexander V. Veidenbaum
2014	—	`conf`	Preface. ICSAMOS Carlo Galuzzi, Alexander V. Veidenbaum
2013	J	`jnl`	Compiler-Assisted, Selective Out-Of-Order Commit. IEEE Comput. Archit. Lett. Nam Duong, Alexander V. Veidenbaum
2013	C	`conf`	Effective Evaluation of Multi-core Based Systems. ISPDC Rosario Cammarota, Laleh Aghababaie Beni, Alexandru Nicolau, Alexander V. Veidenbaum
2013	B	`conf`	On the Determination of Inlining Vectors for Program Optimization. CC Rosario Cammarota, Alexandru Nicolau, Alexander V. Veidenbaum, Arun Kejariwal, Debora Donato, Mukund Madhugiri
2013	—	`conf`	Optimizing Program Performance via Similarity, Using a Feature-Agnostic Approach. APPT Rosario Cammarota, Laleh Aghababaie Beni, Alexandru Nicolau, Alexander V. Veidenbaum
2013	—	`conf`	Temperature aware thread migration in 3D architecture with stacked DRAM. ISQED Dali Zhao, Houman Homayoun, Alexander V. Veidenbaum
2012	Misc	`conf`	A fault tolerant self-scheduling scheme for parallel loops on shared memory systems. HiPC Yizhuo Wang, Alexandru Nicolau, Rosario Cammarota, Alexander V. Veidenbaum
2012	A*	`conf`	Improving Cache Management Policies Using Dynamic Reuse Distances. MICRO Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum
2012	—	`conf`	Just in Time Load Balancing. LCPC Rosario Cammarota, Alexandru Nicolau, Alexander V. Veidenbaum
2012	Misc	`conf`	Revisiting level-0 caches in embedded processors. CASES Nam Duong, Taesu Kim, Dali Zhao, Alexander V. Veidenbaum
2012	—	`conf`	Selective search of inlining vectors for program optimization. Conf. Computing Frontiers Rosario Cammarota, Arun Kejariwal, Debora Donato, Alexandru Nicolau, Alexander V. Veidenbaum
2011	J	`jnl`	MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. IEEE Trans. Very Large Scale Integr. Syst. Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari
2011	J	`jnl`	On leakage power optimization in clock tree networks for ASICs and general-purpose processors. Sustain. Comput. Informatics Syst. Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi
2011	—	`conf`	Pruning hardware evaluation space via correlation-driven application similarity analysis. Conf. Computing Frontiers Rosario Cammarota, Arun Kejariwal, Paolo D'Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, Alexandru Nicolau
2011	J	`jnl`	Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management. IEEE Trans. Very Large Scale Integr. Syst. Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum
2010	—	`conf`	Exploitation of nested thread-level speculative parallelism on multi-core systems. Conf. Computing Frontiers Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos
2010	A	`conf`	Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum
2010	—	`ed.`	International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2010, Hilo, Kohala Coast, HI, USA, January 17-19, 2010 IWIA Kazuki Joe, Alexander V. Veidenbaum
2010	—	`conf`	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. Conf. Computing Frontiers Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt
2010	—	`conf`	On the efficacy of call graph-level thread-level speculation. WOSP/SIPEW Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos
2010	—	`conf`	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. ISQED Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi
2010	—	`conf`	RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. HiPEAC Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil D. Dutt
2009	J	`jnl`	A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum
2009	J	`jnl`	Brain Derived Vision Algorithm on High Performance Architectures. Int. J. Parallel Program. Jayram Moorkanikara Nageswaran, Andrew Felch, Ashok Chandrasekhar, Nikil D. Dutt, Richard Granger, Alex Nicolau, Alexander V. Veidenbaum
2009	Misc	`conf`	Cache-aware partitioning of multi-dimensional iteration spaces. SYSTOR Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
2009	B	`conf`	Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. ICPP Arun Kejariwal, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos
2009	B	`conf`	Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. IJCNN Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum
2009	J	`jnl`	On the exploitation of loop-level parallelism in embedded applications. ACM Trans. Embed. Comput. Syst. Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito
2009	—	`conf`	Performance Characterization of Itanium® 2-Based Montecito Processor. SPEC Benchmark Workshop Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy
2009	A	`conf`	Power-aware load balancing of large scale MPI applications. IPDPS Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum
2009	—	`ed.`	Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009 Conf. Computing Frontiers Gearold Johnson, Carsten Trinitis, Georgi Gaydadjiev, Alexander V. Veidenbaum
2009	A	`conf`	Synchronization optimizations for efficient execution on multi-cores. ICS Alexandru Nicolau, Guangqiang Li, Alexander V. Veidenbaum, Arun Kejariwal
2008	A*	`conf`	A Two-Level Load/Store Queue Based on Execution Locality. ISCA Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero
2008	—	`conf`	A centralized cache miss driven technique to improve processor power dissipation. ICSAMOS Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum
2008	A*	`conf`	A distributed processor state management architecture for large-window processors. MICRO Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero
2008	J	`jnl`	A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. Int. J. Embed. Syst. José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum
2008	C	`conf`	Adaptive techniques for leakage power management in L2 cache peripheral circuits. ICCD Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot
2008	B	`conf`	Cache-aware iteration space partitioning. PPoPP Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
2008	—	`conf`	Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core ICSAMOS Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Xinmin Tian, Milind Girkar, Hideki Saito, Utpal Banerjee
2008	A*	`conf`	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. DAC Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum
2008	B	`conf`	Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. LCTES Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum
2008	J	`jnl`	Improving SDRAM access energy efficiency for low-power embedded systems. ACM Trans. Embed. Comput. Syst. Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal
2008	B	`conf`	Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. LCTES Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum
2008	Misc	`conf`	Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. CASES Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum
2008	J	`jnl`	Optimizing CAM-based instruction cache designs for low-power embedded systems. J. Syst. Archit. Juan L. Aragón, Alexander V. Veidenbaum
2008	C	`conf`	ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. ICCD Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum
2007	J	`jnl`	A predictive decode filter cache for reducing power consumption in embedded processors. ACM Trans. Design Autom. Electr. Syst. Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau
2007	Misc	`conf`	A simplified java bytecode compilation system for resource-constrained embedded processors. CASES Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum
2007	A*	`conf`	Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. SIGMETRICS Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum
2007	—	`conf`	Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. PARCO Jeff Furlong, Andrew Felch, Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Alex Nicolau, Alexander V. Veidenbaum, Ashok Chandrashekar, Richard Granger
2007	C	`conf`	Reducing leakage power in peripheral circuits of L2 caches. ICCD Houman Homayoun, Alexander V. Veidenbaum
2007	B	`conf`	Tight analysis of the performance potential of thread speculation using spec CPU 2006. PPoPP Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
2006	Misc	`conf`	Challenges in exploitation of loop parallelism in embedded applications. CODES+ISSS Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito
2006	C	`conf`	Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. ICCD Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum
2006	A	`conf`	On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. ICS Arun Kejariwal, Xinmin Tian, Wei Li, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
2006	—	`conf`	Probablistic Self-Scheduling. Euro-Par Milind Girkar, Arun Kejariwal, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
2005	C	`conf`	A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. ICCD Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
2005	A	`conf`	An asymmetric clustered processor based on value content. ICS Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum
2005	—	`conf`	Decoupled State-Execute Architecture. ISHPC Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero
2005	—	`conf`	Energy-Effective Instruction Fetch Unit for Wide Issue Processors. Asia-Pacific Computer Systems Architecture Conference Juan L. Aragón, Alexander V. Veidenbaum
2005	Misc	`conf`	High performance annotation-aware JVM for Java cards. EMSOFT Ana Azevedo, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau
2005	J	`jnl`	Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. IEEE Trans. Computers Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta
2005	—	`conf`	Using a Way Cache to Improve Performance of Set-Associative Caches. ISHPC Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau
2004	A*	`conf`	A Content Aware Integer Register File Organization. ISCA Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
2004	J	`jnl`	A partitioned instruction queue to reduce instruction wakeup energy. Int. J. High Perform. Comput. Netw. Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
2004	—	`conf`	An Optimized Front-End Physical Register File with Banking and Writeback Filtering. PACS Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero
2004	B	`conf`	Caching Values in the Load Store Queue. MASCOTS Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau
2004	A	`conf`	Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. DATE Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu
2004	J	`jnl`	Guest Editor's Introduction: Application-Specific Processors. IEEE Micro Alexander V. Veidenbaum
2004	J	`jnl`	Instructions-Wake-Up mechanism: Power and Timing Evaluation. Res. Comput. Sci. Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Marco A. Ramírez, Mateo Valero
2004	C	`conf`	Low Energy, Highly-Associative Cache Design for Embedded Processors. ICCD Alexander V. Veidenbaum, Dan Nicolaescu
2003	—	`conf`	A Data Cache with Dynamic Mapping. LCPC Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum
2003	—	`conf`	A Simple Low-Energy Instruction Wakeup Mechanism. ISHPC Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero
2003	—	`conf`	Energy Aware Register File Implementation through Instruction Predecode. ASAP José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez
2003	J	`jnl`	Guest Editors' Introduction: Application-Specific Microprocessors. IEEE Des. Test Comput. Alex Orailoglu, Alexander V. Veidenbaum
2003	—	`ed.`	High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings ISHPC Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso
2003	C	`conf`	Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. ICCD Sudeep Pasricha, Alexander V. Veidenbaum
2003	—	`ch.`	Low Energy Associative Data Caches for Embedded Systems. Embedded Software for SoC Dan Nicolaescu, Alexander V. Veidenbaum, Alex Nicolau
2003	J	`jnl`	Power-Aware Compilation for Register File Energy Reduction. Int. J. Parallel Program. José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo
2003	A	`conf`	Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. DATE Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau
2003	A	`conf`	Reducing data cache energy consumption via cached load/store queue. ISLPED Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau
2002	J	`jnl`	Guest Editor's Introduction. Int. J. Parallel Program. Alexander V. Veidenbaum
2002	—	`conf`	Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. ISHPC Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
2002	A	`conf`	Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. DATE Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau
2001	J	`jnl`	Guest Editor's Introduction. Int. J. Parallel Program. Alexander V. Veidenbaum
2000	—	`conf`	Compiler-Directed Cache Assist Adaptivity. ISHPC Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
2000	—	`conf`	Compiler-Directed Cache Line Size Adaptivity. Intelligent Memory Systems Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
2000	J	`jnl`	On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors. J. Supercomput. Sunil Kim, Alexander V. Veidenbaum
2000	A	`ed.`	Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000 ICS John Reynders, Alexander V. Veidenbaum
1999	A	`conf`	Adapting cache line size to application behavior. International Conference on Supercomputing Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau, Xiaomei Ji
1999	J	`jnl`	An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. Int. J. Parallel Program. Edward H. Gornish, Alexander V. Veidenbaum
1999	J	`jnl`	Interconnection network organization and its impact on performance and cost in shared memory multiprocessors. Parallel Comput. Sunil Kim, Alexander V. Veidenbaum
1999	J	`jnl`	Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors. Int. J. High Speed Comput. Alexander V. Veidenbaum, Qingbo Zhao, Abduhl Shameer
1998	—	`conf`	Retrospective: The Cedar System. 25 Years ISCA: Retrospectives and Reprints Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan
1997	—	`conf`	Instruction Cache Prefetching Using Multilevel Branch Prediction. ISHPC Alexander V. Veidenbaum
1997	B	`conf`	Stride-directed Prefetching for Secondary Caches. ICPP Sunil Kim, Alexander V. Veidenbaum
1997	—	`conf`	The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems. IEEE PACT Sunil Kim, Alexander V. Veidenbaum
1995	J	`jnl`	Combining flow and dependence analyses to expose redundant array accesses. Int. J. Parallel Program. Elana D. Granston, Alexander V. Veidenbaum
1995	B	`conf`	On Shortest Path Routing in Single Stage Shuffle-Exchange Networks. SPAA Sunil Kim, Alexander V. Veidenbaum
1994	—	`conf`	An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. ICPP (2) Edward H. Gornish, Alexander V. Veidenbaum
1994	A	`conf`	Scalability of the Cedar system. SC Stephen W. Turner, Alexander V. Veidenbaum
1993	—	`conf`	Performance Evaluation of Memory Caches in Multiprocessors. ICPP (1) Yung-Chin Chen, Alexander V. Veidenbaum
1993	A*	`conf`	The Cedar System and an Initial Performance Study. ISCA David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle A. Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, Ulrike Meier Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay P. Hoeflinger, Greg P. Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner
1992	A	`conf`	An Effective Write Policy for Software Coherence Schemes. SC Yung-Chin Chen, Alexander V. Veidenbaum
1991	A	`conf`	A software coherence scheme with the assistance of directories. ICS Yung-Chin Chen, Alexander V. Veidenbaum
1991	—	`conf`	An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems. ICPP (2) Elana D. Granston, Alexander V. Veidenbaum
1991	—	`conf`	Chief: A Parallel Simulation Environment for Parallel Systems. IPPS John D. Bruner, Hoichi Cheong, Alexander V. Veidenbaum, Pen-Chung Yew
1991	A	`conf`	Comparison and analysis of software and directory coherence schemes. SC Yung-Chin Chen, Alexander V. Veidenbaum
1991	A	`conf`	Detecting redundant accesses to array data. SC Elana D. Granston, Alexander V. Veidenbaum
1991	—	`conf`	Preliminary Performance Analysis of the Cedar Multiprocessor Memory System. ICPP (1) Kyle A. Gallivan, William Jalby, Stephen W. Turner, Alexander V. Veidenbaum, Harry A. G. Wijshoff
1991	—	`conf`	The Organization of the Cedar System. ICPP (1) Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter
1990	J	`jnl`	Compiler-Directed Cache Management in Multiprocessors. Computer Hoichi Cheong, Alexander V. Veidenbaum
1990	A	`conf`	Compiler-directed data prefetching in multiprocessors with memory hierarchies. ICS Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum
1989	A	`conf`	A version control approach to Cache coherence. ICS Hoichi Cheong, Alexander V. Veidenbaum
1988	A*	`conf`	A Cache Coherence Scheme With Fast Selective Invalidation. ISCA Hoichi Cheong, Alexander V. Veidenbaum
1988	A	`conf`	Performance of a shared memory system for vector multiprocessors. ICS Stephen W. Turner, Alexander V. Veidenbaum
1988	—	`conf`	Stale Data Detection and Coherence Enforcement Using Flow Analysis. ICPP (1) Hoichi Cheong, Alexander V. Veidenbaum
1987	A	`conf`	The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs. ICS Hoichi Cheong, Alexander V. Veidenbaum
1986	B	`conf`	A Compiler-Assisted Cache Coherence Solution for Multiprcessors. ICPP Alexander V. Veidenbaum