Alexander V. Rylyakov

64 papers Journal 26Unranked 38

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	802 Gbps Coherent Optical Sub-Assembly (COSA) based on a Coupling Modulated Silicon Ring Resonator. BCICTS X. Chen, Ajay Mistry, A. El Sayed, C. Williams, Lorenzo Iotti, A. Atef, Kishore Padmaraju, M. Malinowski, D. Che, Rafid A. Sukkar, Rick Younce, Alexandre Horth, Yury Dziashko, H. Guan, R. Shi, D. Gill, A. Seyoum, C. Marsh, M. Schmidt, G. Burrell, J. Basak, D. Chapman, A. Mikami, Alexander V. Rylyakov, A. Leven, Nicolas A. F. Jaeger
2023	J	`jnl`	A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength. IEEE J. Solid State Circuits Abdelrahman H. Ahmed, Leonardo Vera, Lorenzo Iotti, Ruizhi Shi, Sudip Shekhar, Alexander V. Rylyakov
2020	J	`jnl`	A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength. IEEE J. Solid State Circuits Abdelrahman H. Ahmed, Abdellatif Elmoznine, Daihyun Lim, Yangjin Ma, Alexander V. Rylyakov, Sudip Shekhar
2019	J	`jnl`	34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers. IEEE J. Solid State Circuits Mostafa Gamal Ahmed, Tam N. Huynh, Christopher Williams, Yong Wang, Pavan Kumar Hanumolu, Alexander V. Rylyakov
2019	—	`conf`	A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter. ISSCC Abdelrahman H. Ahmed, Daihyun Lim, Abdellatif Elmoznine, Yangjin Ma, Tam N. Huynh, Christopher Williams, Leonardo Vera, Yang Liu, Ruizhi Shi, Matthew Streshinsky, Ari Novack, Ran Ding, Rick Younce, Rafid A. Sukkar, Jose Roman, Michael Hochberg, Sudip Shekhar, Alexander V. Rylyakov
2019	—	`conf`	An All-Silicon Transmitter with Co-Designed Modulator and DC-Coupled Driver. OFC Yangjin Ma, Christopher Williams, Mostafa Gamal Ahmed, Abdellatif Elmoznine, Daihyun Lim, Yang Liu, Ruizhi Shi, Tam N. Huynh, Jose Roman, Abdelrahman H. Ahmed, Leonardo Vera, Yaojia Chen, Alexandre Horth, Hang Guan, Kishore Padmaraju, Matthew Streshinsky, Ari Novack, Rafid A. Sukkar, Rick Younce, Alexander V. Rylyakov, Dominick Scordo, Michael Hochberg
2019	—	`conf`	Monolithically-Integrated 50 Gbps 2pJ/bit Photoreceiver with Cherry-Hooper TIA in 250nm BiCMOS Technology. OFC Hector Andrade, Takako Hirokawa, Aaron Maharry, Alexander V. Rylyakov, Clint L. Schow, James F. Buckwalter
2018	J	`jnl`	A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. IEEE J. Solid State Circuits Mostafa Gamal Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, Guanghua Shu, Ahmed Elmallah, Alexander V. Rylyakov, Pavan Kumar Hanumolu
2018	—	`conf`	A 34Gbaud Linear Transimpedance Amplifier with Automatic Gain Control for 200Gb/s DP-16QAM Optical Coherent Receivers. OFC Mostafa Gamal Ahmed, Tam N. Huynh, Christopher Williams, Yong Wang, Rahul Shringarpure, Reza Yousefi, Jose Roman, Noam Ophir, Alexander V. Rylyakov
2018	—	`conf`	A Silicon Photonic Transceiver and Hybrid Tunable Laser for 64 Gbaud Coherent Communication. OFC Ari Novack, Matthew Streshinsky, Tam N. Huynh, Tal Galfsky, Hang Guan, Yang Liu, Yangjin Ma, Ruizhi Shi, Alexandre Horth, Yaojia Chen, Amir Hanjani, Jose Roman, Yury Dziashko, Ran Ding, Saeed Fathololoumi, Andy Eu-Jin Lim, Kishore Padmaraju, Rafid A. Sukkar, Rick Younce, Harald Rohde, Robert Palmer, Guido Saathoff, Torsten Wuth, Marc Bohn, Abdelrahman H. Ahmed, Mostafa Gamal Ahmed, Christopher Williams, Daihyun Lim, Abdellatif Elmoznine, Alexander V. Rylyakov, Tom Baehr Jones, Peter Magill, Dominick Scordo, Michael Hochberg
2016	—	`conf`	10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. ISSCC Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
2016	—	`conf`	3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. ISSCC Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli
2015	—	`conf`	10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman
2015	—	`conf`	22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. ISSCC Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli
2015	J	`jnl`	A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2015	J	`jnl`	A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. IEEE J. Solid State Circuits Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli
2015	—	`conf`	A 25 Gb/s burst-mode receiver for low latency photonic switch networks. OFC Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Clint Schow, Mounir Meghelli
2015	—	`conf`	A 4-λ, 40Gb/s/λ bandwidth extension of multimode fiber in the 850nm range. OFC Daniel M. Kuchta, Tam N. Huynh, Fuad E. Doany, Alexander V. Rylyakov, Clint L. Schow, Petar K. Pepeljugoski, D. Gazula, Edward Shaw, Jim Tatum
2015	—	`conf`	A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. OFC Anand Ramaswamy, Jonathan E. Roth, Erik J. Norberg, Robert S. Guzzon, Jae-Hyuk Shin, J. T. Imamura, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish, Benjamin G. Lee, Renato Rimolo-Donadio, Christian W. Baks, Alexander V. Rylyakov, Jonathan E. Proesel, Mounir Meghelli, Clint L. Schow
2015	—	`conf`	A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. OFC Benjamin G. Lee, Renato Rimolo-Donadio, Alexander V. Rylyakov, Jonathan E. Proesel, John F. Bulzacchelli, Christian W. Baks, Mounir Meghelli, Clint L. Schow, Anand Ramaswamy, Jonathan E. Roth, Jae-Hyuk Shin, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish
2015	—	`conf`	High speed circuits for short reach optical communications. OFC Alexander V. Rylyakov
2014	—	`conf`	30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits. OFC Nicolas Dupuis, Benjamin G. Lee, Jonathan E. Proesel, Alexander V. Rylyakov, Renato Rimolo-Donadio, Christian W. Baks, Clint L. Schow, Anand Ramaswamy, Jonathan E. Roth, Robert S. Guzzon, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish
2014	—	`conf`	64Gb/s transmission over 57m MMF using an NRZ modulated 850nm VCSEL. OFC Daniel M. Kuchta, Alexander V. Rylyakov, Clint L. Schow, Jonathan E. Proesel, Christian W. Baks, Petter Westbergh, Johan S. Gustavsson, Anders Larsson
2014	—	`conf`	A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2014	J	`jnl`	A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman
2014	J	`jnl`	A Throughput-Optimized Optical Network for Data-Intensive Computing. IEEE Micro Laurent Schares, Benjamin G. Lee, Fabio Checconi, Russell A. Budd, Alexander V. Rylyakov, Nicolas Dupuis, Fabrizio Petrini, Clint Schow, Pablo Fuentes, Oliver Mattes, Cyriel Minkenberg
2014	—	`conf`	Exploring the limits of high-speed receivers for multimode VCSEL-based optical links. OFC Nicolas Dupuis, Daniel M. Kuchta, Fuad E. Doany, Alexander V. Rylyakov, Jonathan E. Proesel, Christian W. Baks, Clint L. Schow, S. Luong, C. Xie, L. Wang, S. Huang, K. Jackson, N. Y. Li
2014	—	`conf`	Low power CMOS-driven 1060 nm multimode optical link. OFC Jean Benoit Héroux, Tomofumi Kise, Masaki Funabashi, Toyohiro Aoki, Clint Schow, Alexander V. Rylyakov, Shigeru Nakagawa
2013	J	`jnl`	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	A 56.1Gb/s NRZ modulated 850nm VCSEL-based optical link. OFC/NFOEC Daniel M. Kuchta, Clint L. Schow, Alexander V. Rylyakov, Jonathan E. Proesel, Fuad E. Doany, Christian W. Baks, B. H. Hamel-Bissell, Chris Kocot, L. Graham, R. Johnson, Gary Landry, E. Shaw, A. MacInnes, Jim Tatum
2013	J	`jnl`	A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
2013	J	`jnl`	Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits. OFC/NFOEC Benjamin G. Lee, Alexander V. Rylyakov, William M. J. Green, Solomon Assefa, Christian W. Baks, Renato Rimolo-Donadio, Daniel M. Kuchta, Marwan H. Khater, Tymon Barwicz, Carol Reinholm, Edward Kiewra, Steven M. Shank, Clint L. Schow, Yurii A. Vlasov
2013	—	`conf`	Monolithically integrated silicon nanophotonics receiver in 90nm CMOS technology node. OFC/NFOEC Solomon Assefa, Huapu Pan, Steven Shank, William M. J. Green, Alexander V. Rylyakov, Clint Schow, Marwan Khater, Swetha Kamlapurkar, Edward Kiewra, Carol Reinholm, Teya Topuria, Philip Rice, Christian W. Baks, Yurii A. Vlasov
2013	—	`conf`	Optical receivers using DFE-IIR equalization. ISSCC Jonathan E. Proesel, Alexander V. Rylyakov, Clint Schow
2012	—	`conf`	25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS. ISSCC Jonathan E. Proesel, Clint Schow, Alexander V. Rylyakov
2012	—	`conf`	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman
2012	J	`jnl`	Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers. IEEE J. Solid State Circuits Alexander V. Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Solomon Assefa, Fuad E. Doany, Min Yang, Joris Van Campenhout, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov
2012	J	`jnl`	Ultra-Low-Power 10 to 285 Gb/s CMOS-Driven VCSEL-Based Optical Links [Invited]. JOCN Jonathan E. Proesel, Benjamin G. Lee, Alexander V. Rylyakov, Christian W. Baks, Clint L. Schow
2011	—	`conf`	A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver. ISSCC Alexander V. Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Joris Van Campenhout, Min Yang, Fuad E. Doany, Solomon Assefa, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov
2011	—	`conf`	Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers. ACM Great Lakes Symposium on VLSI Solomon Assefa, William M. J. Green, Alexander V. Rylyakov, Clint Schow, Folkert Horst, Yurii A. Vlasov
2010	J	`jnl`	An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. IEEE Trans. Very Large Scale Integr. Syst. Montek Singh, José A. Tierno, Alexander V. Rylyakov, Sergey V. Rylov, Steven M. Nowick
2009	—	`conf`	Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
2009	J	`jnl`	Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link. IEEE J. Solid State Circuits Clint L. Schow, Fuad E. Doany, Chen Chen, Alexander V. Rylyakov, Christian W. Baks, Daniel M. Kuchta, Richard A. John, Jeffrey A. Kash
2008	—	`conf`	A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman
2008	J	`jnl`	A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. IEEE J. Solid State Circuits José A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman
2008	—	`conf`	A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. CICC Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman
2008	—	`conf`	A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects. ISSCC Clint Schow, Fuad E. Doany, Chen Chen, Alexander V. Rylyakov, Christian W. Baks, Daniel M. Kuchta, Richard A. John, Jeffrey A. Kash
2007	J	`jnl`	A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. IEEE J. Solid State Circuits Jackie Koon Lun Wong, Alexander V. Rylyakov, Chih-Kong Ken Yang
2007	J	`jnl`	A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. IEEE J. Solid State Circuits Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman
2007	—	`conf`	A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. ISSCC Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli
2006	J	`jnl`	A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
2006	—	`conf`	A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman
2005	J	`jnl`	A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. IEEE J. Solid State Circuits Behnam Analui, Alexander V. Rylyakov, Sergey V. Rylov, Mounir Meghelli, Ali Hajimiri
2004	J	`jnl`	96-GHz static frequency divider in SiGe bipolar technology. IEEE J. Solid State Circuits Alexander V. Rylyakov, Thomas Zwick
2003	—	`conf`	45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. CICC Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman
2003	J	`jnl`	A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. IEEE J. Solid State Circuits Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman
2003	—	`conf`	A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer
2003	J	`jnl`	SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer
2002	J	`jnl`	40-Gb/s circuits built from a 120-GHz f IEEE J. Solid State Circuits Greg G. Freeman, Mounir Meghelli, Young Kwark, Steven Zier, Alexander V. Rylyakov, Michael Sorna, Todd Tanji, Oswin M. Schreiber, Keith Walter, Jae-Sung Rieh, Basanth Jagannathan, Alvin J. Joseph, Seshadri Subbanna
2002	J	`jnl`	50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. IEEE J. Solid State Circuits Mounir Meghelli, Alexander V. Rylyakov, Lei Shan
2002	—	`conf`	An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. ASYNC José A. Tierno, Sergey V. Rylov, Alexander V. Rylyakov, Montek Singh, Steven M. Nowick